Multi-shifting shift register

Details Multi-shifting shift register Multi-shifting shift register

2001-05-02

2002-10-01

Wambach, Margaret R. (Department: 2816)

Electrical pulse counters, pulse dividers, or shift registers: c

Applications

Including memory

C377S043000, C377S078000

Reexamination Certificate

active

06459751

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The invention relates to a shift register, more particularly to a multi-shifting shift register.
2. Description of the Related Art
FIG. 1
illustrates a conventional shift register for outputting a selected address signal to a memory array (not shown). The selected address signal is capable of enabling a corresponding word line of the memory array for data storage and access. The conventional shift register includes a plurality of ring-cascaded D-type flip-flops. In this example, there are four D-type flip-flops (DEF
0
, DEF
1
, DEF
2
, DEF
3
). Each of the flip-flops (DEF
0
, DEF
1
, DEF
2
, DEF
3
) has an input (D), a timing pulse signal input (T) for receiving a timing pulse signal (Clock), and an output (Q) for generating an address signal (AD(
0
), AD(
1
), AD(
2
), AD(
3
)). The input of each of the flip-flops (DEF
0
, DEF
1
, DEF
2
, DEF
3
) is connected to the output (Q) of a preceding one of the flip-flops (DEF
0
, DEF
1
, DEF
2
, DEF
3
) . Due to a positive-edge triggering action (i.e. logic-low to logic-high transition) of the time pulse signal (Clock), the address signal previously received by the input (D) of each flip-flop is outputted at the output (Q) of the same.
Before the conventional shift register starts working, each of the flip-flops (DFF
0
, DFF
1
, DFF
2
, DFF
3
) should be reset. During a first cycle
11
of the timing pulse signal (Clock), a logic-high reset signal (Reset) (see
FIG. 2
b
) is received by the flip-flops (DFF
0
, DFF
1
, DFF
2
, DFF
3
) for clearing data therein such that only the address signal (AD(
0
)) outputted at the output (D) of the first flip-flop (DFF(
0
)) is at a logic-high state, as shown in
FIG. 2
c
, and such that the other address signals (AD(
1
), AD(
2
), AD(
3
)) are at a logic-low state. During a second cycle
12
of the timing pulse signal (Clock), the logic-high address signal (AD(
0
)) received by the input (D) of the second flip-flop (DFF
1
) is outputted at the output (Q) of the second flip-flop (DFF
1
) such that the address signal (AD(
1
)) is at the logic-high state, as shown in
FIG. 2
d
. During a third cycle
13
of the timing pulse signal (Clock), the address signal (AD(
2
)) outputted at the output (Q) of the third flip-flop (DFF
2
) is at the logic-high state, and the other address signals (AD(
0
), AD(
1
), AD(
3
)) are at the logic-low state. During a fourth cycle
14
of the timing pulse signal (Clock), the address signal (AD(
3
)) outputted at the output (Q) of the fourth flip-flop (DFF
3
) is at the logic-high state, and the other address signals (AD(
0
), AD(
1
), AD(
2
)) are at the logic-low state. Therefore, the selected address signal outputted by the conventional shift register is shifted by only one position during each cycle of the timing pulse signal (Clock).
Thus, according to the conventional shift register, when the selected address signal is required to be shifted by two positions, an operation time equal to two cycles of the timing pulse signal (Clock) is necessary, thereby resulting in a time delay.
SUMMARY OF THE INVENTION
Therefore, the object of the present invention is to provide a multi-shifting shift register that is capable of outputting a selected address signal to a memory unit with minimal time delay as compared to the aforesaid prior art.
According to the present invention, a multi-shifting shift register is adapted for outputting a selected address signal to a memory unit, and comprises:
a control circuit for outputting a number (i) of shift signals and a timing pulse signal, wherein one of the shift signals is at an enabled state and the other ones of the shift signals are at a disabled state during each cycle of the timing pulse signal; and
a multi-shifting circuit including a number (N) of cascaded register units, the number (N) being larger than the number (i), each of the register units having a flip-flop and a selector, the flip-flop having an input end, and an output end for generating an address signal, the selector having the number (i) of select inputs that receive the number (i) of the shift signals respectively from the control circuit, the number (i) of address signal inputs, and an output, the output end of the flip-flop being connected to a first one of the address signal inputs of the selector, the input end of the flip-flop of each of the register units being connected to the output of the selector of a preceding one of the register units, a j
th
one of the address signal inputs of the selector of each of the registers units being connected to the output end of the flip-flop of a (j−1)
th
preceding one of the register units, the number (j) being a number between 2 and I, wherein when a k
th
one of the shift signals that are received at said select inputs of the selector is at the enabled state during a cycle of the timing pulse signal, the selector provides the signal, which is received at a k
th
one of the address signal inputs, at the output thereof, the number (k) being a number between 1 and i;
the selected address signal being the address signal that is outputted by the flip-flop of one of the register units and that is at the enabled state.


REFERENCES:
patent: 6061417 (2000-10-01), Kelem

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