Multi-shelf system clock synchronization

Details Multi-shelf system clock synchronization Multi-shelf system clock synchronization

2007-04-24

2007-04-24

Bayard, Emmanuel (Department: 2611)

Pulse or digital communications

Synchronizers

Self-synchronizing signal

Reexamination Certificate

active

10670304

ABSTRACT:
A method and apparatus for conveying to a control shelf of a multi-shelf network node any master clock signal received via a plurality of interface cards associated with a plurality of peripheral shelves of the multi-shelf network node is presented. The apparatus operating in accordance with the method includes a peripheral shelf controller having: a selector selecting an External SYNChronization (ESYNC) signal from a multitude of ESYNC signals received at an associated peripheral shelf; a comparator deriving phase difference information in comparing the selected ESYNC signal and a SSYNC signal distributed by the control shelf; and encoder for digitally encoding the phase difference information at the peripheral shelf; means for conveying a digital phase difference information digitally between a peripheral shelf and the control shelf. The apparatus further includes a control shelf controller having: a phase difference information stream selector at the control shelf selects a phase difference information stream; an ESYNC regenerator providing to a system synchronization unit an ESYNC signal regenerated from the SSYNC signal and the selected phase difference information stream. Advantages are derived from a scalable synchronization signal infrastructure providing any selected ESYNC signal received via any interface card associated with any peripheral shelf of a multi-shelf network node to the control shelf for synchronizing an SSYNC signal thereto.

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patent: 1 045 557 (2000-10-01), None
patent: 1 326 385 (2003-07-01), None

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