Electrical computers and digital processing systems: processing – Processing architecture – Array processor
Patent
1997-08-14
2000-07-25
Donaghue, Larry D.
Electrical computers and digital processing systems: processing
Processing architecture
Array processor
712 14, 712 11, G06F 944
Patent
active
060947144
DESCRIPTION:
BRIEF SUMMARY
The invention relate s to computers for use with real-time applications and in particular though not exclusively to computers implementing applications involving a high degree of parallel processing and making use of the Prolog language.
One of the major advantages of the radar ESM sensor is its potential ability to accurately identify platforms which are radiating in the radar band through the identification of their radar equipments. To an ESM system designer the term identification usually means the final stage of processing in the software element of an ESM system (the ESM processor). It is therefore seen primarily as a software entity which consists essentially of an ESM library and an identification program or algorithm. The library describes the characteristics of the objects to be identified by the identification algorithm. The library may consist of radar descriptions, radar platform descriptions, or more complex objects. The identification algorithm may be defined as a set of algorithms where, for instance, different algorithms are used for emitter identification. This invention is to be described in relation to emitter identification. Emitter identification is generally interpreted as identification of emitter type. The interpretation can also be extended to include identification of emitter mode and specific radar emitter unit. Current emitter identification algorithms in ESM systems use relatively simple matching techniques to compare ESM tracks against an ESM library containing crude emitter descriptions. Research is currently aimed at devising better identification algorithms using a Knowledge Based Systems (KBS) approach to the analysis of the identification problem and the design of identification algorithms.
While research into the KBS approach has proved to be successful in producing an emitter identification algorithm with greatly improved performance levels, it is recognised that the design of successful advanced research software is not enough in itself to solve the identification problem for practical systems. It is also necessary to provide a vehicle for real-time implementation of advanced identification algorithms.
The inventors have been using a logic programming language Prolog for programming a suitable Knowledge Based System for radar emitter identification. This programme is known as PALANTIR. The PALANTIR program has an emitter library and conducts complex matching of ESM tracks against its emitter library. This matching process takes account of all emitter parameter agility information and reasons about the uncertainty in the ESM track data, the matching process itself and the uncertainty in the emitter library data.
Two levels of response are needed from an operational radar identification system: provision of data to electronic countermeasures systems. This response level is very demanding, even for simple identification systems, particularly if more than one ESM track is to be processed.
The rapid response for threat warning and the complex KBS program PALANTIR make use of Prolog on conventional general-purpose computers ineffective for both levels of response.
The inventors have found that there is no computer architecture available that will provide a very high Prolog execution capability within a real-time environment.
The object of the present invention is to provide a suitable computer capable of exploiting data parallelism to proved high performance real-time Prolog execution.
The invention comprises: a parallel processing computer arranged for direct execution of logic programming language Prolog comprising a plurality of processing nodes: each processing node comprising three central processing units (CPUs), a memory architecture adapted for Prolog execution and interfacing hardware; each processing node being connected to a communications bus and a real-time broadcast bus whereby real-time data from an input can be broadcast via the real-time broadcast bus to each processing node.
One of the CPUs may be directed at the management of communications and scheduling
REFERENCES:
patent: 5163133 (1992-11-01), Nelson et al.
patent: 5247307 (1993-09-01), Olivier et al.
Roe et al., "The Application of Artificial Intelligence Techniques to Naval ESM Radar Indentification" 1994, pp. 565-572.
Practical Application of Prolog. The Proceedings of the Third International Conference on the Practical Application of Prolog, Proceedings PAP'95. The Third International Conference. Practical Application of Prolog, Paris, France, Apr. 3-6, 1995, ISBN-0-9525554-0-9, 1995, Blackpool, UK, Alinmead Software, UK, pp. 281-292, XP000574616 Hawkes R et al: "A real-time Prolog solution for naval ESM radar identification". See the whole document.
Conference on Computer Workstations, Santa Clara, Mar. 7-10, 1988, No. Conf. 2, Mar. 7, 1988, Institute of Electrical and Electronics Engineers, pp. 60-69, XP000092709 Fu H C et al: "A Multi-Processor System for Prolog Processing" see p. 60, right-hand column, line 13--p. 61, right-hand column, line 2; figure 2.1 See paragraph 5, see paragraph 6.
Information Processing, San Francisco, Aug.28-Sep.,1, 1989, No. Congress 11, Aug. 28, 1989, Ritter G X, pp. 627-632, XP000079018, Kazuo Taki: The FGCS Computing Architecture: see paragraph 3.2, see paragraph 3.3, see paragraph 3.4, see paragraph 3.6.
IEE Colloquium on `Signal Processing in Electronic Warfare`)Digest No. 1994/025) IEE Colloquium on `Signal Processing in Electronic Warfare`(Digest No.1994/025), London, UK, Jan. 31, 1994, London UK, IEE, UK, pp. 7/1-6, XP002007332 Roe J et al: "The real-time implementation of emitter identification for ESM" see p. 6, lien 1-line 10.
Michael Alan
Pudner Anthony
Roe Jonathan
Donaghue Larry D.
The Secretary of State for Defence in Her Britannic Majesty's Go
LandOfFree
Multi-sequential computer for real-time applications does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Multi-sequential computer for real-time applications, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Multi-sequential computer for real-time applications will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-1343829