Multi-segmented bus and method of operation

Details Multi-segmented bus and method of operation Multi-segmented bus and method of operation

1995-05-23

1997-05-20

Teska, Kevin J.

395310, G06F 938, G06F 1314

Patent

active

056320299

ABSTRACT:
A multi-level hierarchical bus architecture implemented with a multi-chip package and a modular shared-bus provides high bandwidth. All IC components are mounted on standardized multi-chip packages. Each multi-chip package includes bus interface chips for providing communication from the integrated circuits to a board bus. One multi-chip package contains additional bus interface circuitry for providing communication from the board bus to a backplane bus.

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