Radiation imagery chemistry: process – composition – or product th – Registration or layout process other than color proofing
Reexamination Certificate
1999-12-13
2001-05-22
Young, Christopher G. (Department: 1756)
Radiation imagery chemistry: process, composition, or product th
Registration or layout process other than color proofing
C438S975000, C438S401000
Reexamination Certificate
active
06235437
ABSTRACT:
BACKGROUND OF THE INVENTION
(1) Field of the Invention
The invention relates to the fabrication of integrated circuit devices, and more particularly, to a multi-segment alignment mark that can be used for a variety of lithography masking processes in the fabrication of integrated circuits.
(2) Description of the Prior Art
In the fabrication of integrated circuit devices, multiple layers of conductors and insulators are deposited and patterned to construct the integrated circuit. It is critical to align each subsequent layer with the previous layer with precision. This is typically accomplished by using alignment marks. A wafer stepper tool uses the alignment marks on a wafer as a reference point for adjusting a reticle over the wafer. The reticle contains the pattern to be generated within the layer. The reticle must be precisely aligned to the previous layer. A wafer stepper uses one of at least three methods to detect the alignment marks; these are light interference, bright field contrast, or dark field polarization effect.
For example, wafer alignment on an ASML stepper uses zero marks. For oxide chemical mechanical polishing (CMP) processes, zero marks are distorted at the metal layers due to oxide residue left on the marks. Target repairs at via layers are necessary to ensure that the zero marks are completely clean and can continue to be used. ASML's scribeline primary marks (SPM) have been developed to replace zero marks. The segmentation of the SPM marks determines signal strength and so is an important criteria for good alignment. For a foundry using this alignment scheme, different segmentations must be tested to find an optimized segmentation for each of the different processes. This testing requires laborious effort.
U.S. Pat. No. 5,627,624 to Yim et al shows a test reticle and alignment mark optimization method. U.S. Pat. No. 5,496,777 to Moriyama teaches forming alignment marks in enlarged portions of scribe lines. U.S. Pat. No. 5,401,691 to Caldwell discloses an inverse open frame alignment mark. U.S. Pat. No. 5,369,050 to Kawai discloses an alignment mark having a groove around it. U.S. Pat. No. 5,648,854 to McCoy et al discloses an alignment system using global alignment marks.
SUMMARY OF THE INVENTION
Accordingly, it is a principal object of the present invention to provide an effective and very manufacturable method of generating alignment marks in the manufacture of an integrated circuit device.
A further object of the invention is to provide a method of generating alignment marks useful for a variety of lithography processes.
A still further object is to provide a multi-segment alignment mark useful for a variety of lithography processes.
Another object of the invention is to provide a method of generating alignment marks useful for a variety of lithography processes by using a multi-segment alignment mark incorporating different segmentations into the size of a single mark.
Yet another object is to provide a multi-segment alignment mark incorporating different segmentations into the size of a single mark.
In accordance with the objects of this invention a multi-segment alignment mark useful for a variety of lithography processes is achieved. The multi-segment alignment mark comprises a plurality of segments wherein each of the segments comprises a series of sub-segments wherein each of the sub-segments comprises a series of spaces and lines, each sub-segment having the same width but having a different number of spaces and lines within the width depending on the relative width of the spaces and lines. A wafer stepper detects signals from each of the sub-segments and uses the best signal to achieve alignment.
REFERENCES:
patent: 5369050 (1994-11-01), Kawai
patent: 5401691 (1995-03-01), Caldwell
patent: 5496777 (1996-03-01), Moriyama
patent: 5627624 (1997-05-01), Yim et al.
patent: 5648854 (1997-07-01), McCoy et al.
patent: 5806951 (1998-09-01), Hashimoto
patent: 6022649 (2000-02-01), Neon et al.
Ang Kay Chai
Lam Zadig Cheung-Ching
Neoh Soon Ee
Tan Juan Boon
Chartered Semiconductor Manufacturing Ltd.
Pike Rosemary L. S.
Saile George O.
Young Christopher G.
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