Multi-rate transponder system and chip set

Details Multi-rate transponder system and chip set Multi-rate transponder system and chip set

1999-12-21

2003-10-07

Ton, Dang (Department: 2666)

Multiplex communications

Communication techniques for information carried in plural...

Combining or distributing information via time channels

C375S355000

Reexamination Certificate

active

06631144

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates to a multi-rate transponder system and circuits that support reception and transmission of serial data streams at nominal rates and of transport network rates according to one or several standard communication protocols, such as SDH STM-1/STM-4/STM-16/STM-64 and 1.250 Gbit/s Gigabit Ethernet. The multi-rate transponder circuit may comprise a chip set that implements a front-end in high-speed Optical Network applications thereby providing interconnection between high-speed line interfaces and standard system controllers. These system controllers may be based on CMOS Application Specific Integrated Circuit (ASIC) technology or based on FPGA technology, and thereby unable to directly connect to and support the often required Gbit/s operation of the high-speed line interfaces.
BACKGROUND OF THE INVENTION
In high-speed digital communication systems, transponder chip sets, typically comprising a receiver chip and a transmitter chip, are utilised to amplify and reshape a, typically, distorted signal waveform of an incoming serial data stream or incoming data stream to provide a reshaped outgoing data stream of nominal amplitude. The distortion of the signal waveform is often created by the transmission characteristics, e.g. dispersion and amplitude attenuation, of network cables in the high-speed digital communication system.
In some applications, it is furthermore desirable to be able to receive and transmit data streams at increased bit rates or transport network bit rates as defined in the technical standard ITU-T G.975. According to this standard, data streams may be received and transmitted at a transport network bit rate which is defined as a bit rate that is an odd ratio factor higher than the nominal bit rate of the relevant communication protocol. Thus, data might be transmitted and/or received at the nominal bit rate multiplied with a scaling ratio such as 15/14, 16/15 32/31 etc. Accordingly, any nominal bit rate may have one or several corresponding transport network bit rate(s).
If the nominal bit rate of the utilised communication protocol is 2.488 Gbit/s, which is the case for STM-16, the chip set and the transponder system must be able to receive and transmit data at rates at the corresponding transport network bit rates of 2.666 Gbit/s and 2.568 Gbit/to support 15/14 and 32/31 transport network bit rates, respectively. The overhead data which are provided by the use of the transport network bit rates may be utilised for system level service purposes such as monitoring error rates of the data streams between network nodes and/or correcting errors using forward error correcting schemes according to ITU-T G.975. The overhead data may also be utilised for transmitting dedicated data belonging to the network operator together with ordinary transport stream data between network nodes. It is furthermore often required that the chip set and the transponder system should be capable of supporting reception/transmission of data streams at nominal bit rates of several differing communication protocols e.g. SDH STM-1, STM-4, STM-16, STM-64 etc.
Accordingly, it is desirable to provide a single transponder circuit, preferably as a chip set, and a corresponding transponder system that both support multi-rate data stream reception/transmission and also support one or several transport network bit rates at each selected nominal bit rate.
SUMMARY OF THE INVENTION
One object of the invention is to provide a single multi-rate transponder circuit, preferably as a chip set, and a corresponding multi-rate transponder system that are capable of supporting multi-rate reception and transmission of incoming and outgoing serial data streams, respectively, and furthermore support reception and transmission of transport network bit rates.
According to one aspect of the. invention, there is provided a multi-rate transponder system that is capable of receiving the incoming data stream at a nominal bit rate or at a corresponding transport network bit rate and wherein the bit rate of the outgoing serial data stream or outgoing data stream is independently selectable as either the nominal bit rate or the transport network bit rate.
DESCRIPTION OF THE INVENTION
A first aspect of the invention relates to a multi-rate transponder system for receiving an incoming data stream and transmitting an outgoing serial data stream, the multi-rate transponder system comprising:
a receiving part, a system controller and a transmitting part;
the receiving part comprising:
a Clock and Data Recovery (CDR) circuit adapted to receive the incoming serial data stream at a nominal bit rate or at a corresponding transport network bit rate, the CDR circuit being adapted to derive a clock signal and a data signal from the incoming serial data stream, and
a data transfer circuit adapted to generate an incoming data signal based on the derived data signal on one or several data transfer channels, and
a clock transfer circuit adapted to generate a receiver clock signal on a receiver clock line, and
a reference clock circuit adapted to generate a reference clock signal for the transmitting part based on a clock signal associated with the incoming serial data stream,
the system controller comprising:
system data receiving means, system data transfer means, system data processing means and a slide-buffer,
the system data receiving means being adapted to receive the incoming data signal from the one or several data transfer channels and the receiver clock signal from the receiver clock line and to provide the incoming data signal to the slide-buffer for clock domain transfer, and
the system data processing means being adapted to process the incoming data signal in the slide-buffer by inserting data bits into the incoming data signal and/or extracting data bits from the incoming data signal and/or monitoring data bits in the incoming data signal to generate an outgoing data signal to the system data transfer means on one or several data transfer channels, and
the system data transfer means being adapted to provide the outgoing data signal to the transmitting part in response to a transmitter clock signal provided on a transmitter clock line,
the transmitting part comprising:
a transmitter Phase Locked Loop (PLL) adapted to receive and lock onto the reference clock signal and to generate an output clock signal based on the reference clock signal,
a transmitter clock circuit adapted to generate the transmitter clock signal to the system data transfer means,
a data reception circuit adapted to receive the outgoing data signal from the system data transfer means and to generate the serial outgoing data stream at the nominal bit rate or at the corresponding transport network bit rate independently of the bit rate of the incoming serial data stream, based on the outgoing data signal and the output clock signal.
In the present specification and claims the term “nominal bit rate” designates a bit rate that equals a bit rate of a standardised communication protocol. As an example, if the present multi-rate transponder circuit or system is adapted to support communication according to SDH STM-16, the nominal bit rate equals 2.488 Gbit/s. The term “transport network bit rate” designates a bit rate of a data stream that is increased with a scaling ratio relative to a corresponding nominal bit rate of that data stream. A number of standardised transport network bit rates associated with a nominal bit rate is recommended by ITU-T G.975. According to this standard, a transport network bit rate equals the nominal bit rate multiplied with a number of selectable odd ratio factors.
According to the present invention, the system controller may be comprise a proprietary microprocessor or a commercially available microprocessor and associated logic circuitry. The system controller may also be provided as an ASIC that comprises a fully proprietary microprocessor or a commercially available embedded microprocessor core or kernel integrated with custom designed logic circuitry. In some applications it may be

Affiliated with

Also associated with

Rating

Multi-rate transponder system and chip set does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Multi-rate transponder system and chip set, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Multi-rate transponder system and chip set will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-3145708