Coded data generation or conversion – Digital code to digital code converters – Serial to parallel
Reexamination Certificate
2006-08-15
2006-08-15
Jeanglaude, Jean Bruner (Department: 2819)
Coded data generation or conversion
Digital code to digital code converters
Serial to parallel
C341S059000
Reexamination Certificate
active
07091890
ABSTRACT:
A serializer-deserializer instantiated in configurable logic of an integrated circuit is described. The serializer-deserializer includes an input deserializer and an output serializer, which may be commonly coupled via an input/output pad. Each of the serializer and deserializer may be configured for an operating mode selected from a Single Data Rate mode and a Double Data Rate mode. The serializer-deserializer may be used as part of a synchronous interface.
REFERENCES:
patent: 4688016 (1987-08-01), Fok
patent: 5038365 (1991-08-01), Belloc et al.
patent: 6459393 (2002-10-01), Nordman
patent: 6542096 (2003-04-01), Chan et al.
patent: 6671787 (2003-12-01), Kanda et al.
patent: 6707399 (2004-03-01), Wang et al.
patent: 2003/0193894 (2003-10-01), Tucker et al.
patent: 2004/0243899 (2004-12-01), Bonneau et al.
U.S. Appl. No. 10/889,553, filed Jul. 12, 2004, Zhang et al.
U.S. Appl. No. 10/889,248, filed Jul. 12, 2004, Zhang et al.
U.S. Appl. No. 10/919,766, filed Aug. 17, 2004, Sasaki et al.
U.S. Appl. No. 10/919,900, filed Aug. 17, 2004, Sasaki et al.
Altera, Corp., “QDR SRAM Controller Reference Design for Stratix and Stratix GS Devices”, Application Note 211, Nov. 2002, pp. 1-30, v. 2.0, available from Altera Corporation, 2610 Orchard Parkway, San Jose, California 95134-2020.
Altera, Corp., “The Benefits of Altera's High-Speed DDR SDRAM memory Interface Solution”, White Paper, May 2004, pp. 1-16, v. 1.1 available from Altera Corporation, 2610 Orchard Parkway, San Jose, California 95134-2020.
Altera, Corp., “DDR SDRAM Controller MegaCore Function User Guide”, Feb. 2003, pp. 1-89, Core Version 1.1.0, Document Version 1.1.0 rev 1, available from Altera Corporation, 2610 Orchard Parkway, San Jose, California 95134-2020.
Altera, Corp., “Using High-Speed Differential I/O Interfaces in Stratix Devices”, Application Note 202, Jan. 2003, pp. 1-72, v. 2.1, available from Altera Corporation, 2610 Orchard Parkway, San Jose, California 95134-2020.
Altera, Corp., “Using Source-Synchronous Signaling with DPA in Stratix GX Devices”, Application Note 236, Nov. 2002, pp. 1-18, v. 1.0, available from Altera Corporation, 2610 Orchard Parkway, San Jose, California 95134-2020.
Altera, Corp., “Section 1. Device Pine Information”, Jul. 2003, Ch. 1-7, pp. 1-1 to 7-84, v. 2.0, available from Altera Corporation, 2610 Orchard Parkway, San Jose, California 95134-2020.
Altera, Corp., “Section II. Memory”, Apr. 2004, Ch. 2-3, pp. II-1 to 3-28, v. 3.0, available from Altera Corporation, 2610 Orchard Parkway, San Jose, California 95134-2020.
Altera, Corp., “Section III. I/O Standards”, Apr. 2004, Ch. 4-5, pp. III-1 to 5-76, v. 3.0, available from Altera Corporation, 2610 Orchard Parkway, San Jose, California 95134-2020.
Altera, Corp., “Section VI. Configuration & Remote System Upgrades”, Apr. 2004, Ch. 11-12, pp. VI-1 to 12-44, available from Altera Corporation, 2610 Orchard Parkway, San Jose, California 95134-2020.
Altera, Corp., “2. TriMatrix Embedded Memory Blocks in Stratix & Stratix GX Devices”, Apr. 2004, pp. 2-1 to 2-28, v. 3.0, available from Altera Corporation, 2610 Orchard Parkway, San Jose, California 95134-2020.
Altera, Corp., “3. External Memory Interfaces”, Apr. 2004, pp. 3-1 to 3-28, v. 3.0, available from Altera Corporation, 2610 Orchard Parkway, San Jose, California 95134-2020.
Altera, Corp., “4. Selectable I/O Standards in Stratix & Stratix GX Devices”, Apr. 2004, pp. 4-1 to 4-42, vol. 2, v. 3.0, available from Altera Corporation, 2610 Orchard Parkway, San Jose, California 95134-2020.
Altera, Corp., “5. High-Speed Differential I/O Interfaces in Stratix Devices”, Apr. 2004, pp. 5-1 to 5-76, vol. 2, v. 3.0, available from Altera Corporation, 2610 Orchard Parkway, San Jose, California 95134-2020.
Altera, Corp., “Section I. Clock Management”, Apr. 2004, pp. 1-1 to 1-58, vol. 2, v. 3.0, available from Altera Corporation, 2610 Orchard Parkway, San Jose, California 95134-2020.
Altera, Corp., “Section I. Stratix Device Family Data Sheet”, Apr. 2004, Ch. 1-5, pp. 1-1 to 5-2, vol. 1, available from Altera Corporation, 2610 Orchard Parkway, San Jose, California 95134-2020.
Altera, Corp., “Section II. PCB Layout Guidelines”, Apr. 2003, Ch. 8-10, pp. II-1 to 10-58, vol. 1, available from Altera Corporation, 2610 Orchard Parkway, San Jose, California 95134-2020.
Bazargan Hassan
Bergendahl Jason R.
Ghia Atul
Menon Suresh
Sasaki Paul T.
Liu Justin
Webostad W. Eric
Xilinx , Inc.
LandOfFree
Multi-purpose source synchronous interface circuitry does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Multi-purpose source synchronous interface circuitry, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Multi-purpose source synchronous interface circuitry will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3712278