Miscellaneous active electrical nonlinear devices – circuits – and – Signal converting – shaping – or generating – Frequency or repetition rate conversion or control
Reexamination Certificate
2002-11-26
2004-03-30
Le, Dinh T. (Department: 2816)
Miscellaneous active electrical nonlinear devices, circuits, and
Signal converting, shaping, or generating
Frequency or repetition rate conversion or control
C327S117000, C377S047000
Reexamination Certificate
active
06714057
ABSTRACT:
FIELD OF THE INVENTION
The invention relates to digital frequency synthesizer (DFS) circuits for clocked digital systems. More particularly, the invention relates to a simple but flexible DFS circuit having particularly advantageous application to a Programmable Logic Device (PLD).
BACKGROUND OF THE INVENTION
Programmable logic devices (PLDs) are a well-known type of digital integrated circuit that can be programmed to perform specified logic functions. One type of PLD, the field programmable gate array (FPGA), typically includes an array of configurable logic blocks (CLBs) surrounded by a ring of programmable input/output blocks (IOBs). The CLBs and IOBs are interconnected by a programmable interconnect structure. Some FPGAs also include additional logic blocks with special purposes (e.g., DLLs, RAM, and so forth).
The CLBS, IOBS, interconnect, and other logic blocks are typically programmed by loading a stream of configuration data (bitstream) into internal configuration memory cells that define how the CLBs, IOBs, and interconnect are configured. The configuration data can be read from memory (e.g., an external PROM) or written into the FPGA by an external device. The collective states of the individual memory cells then determine the function of the FPGA.
Another type of PLD is the Complex Programmable Logic Device, or CPLD. A CPLD includes two or more programmable function blocks connected together and to input/output (I/O) resources by an interconnect switch matrix. Each function block of the CPLD includes a two-level AND/OR structure similar to those used in Programmable Logic Arrays (PLAS) and Programmable Array Logic (PAL) devices. In some CPLDs, configuration data is stored on-chip in non-volatile memory, then downloaded to volatile memory as part of an initial configuration sequence.
For all of these programmable logic devices (PLDs), the functionality of the device is controlled by data bits provided to the device for that purpose. The data bits can be stored in volatile memory (e.g., static RAM cells, as in FPGAs and some CPLDs), in non-volatile memory (e.g., FLASH memory, as in some CPLDs), or in any other type of memory cell.
Other PLDs are programmed by applying a processing layer, such as a metal layer, that programmably interconnects the various elements on the device. These PLDs are known as ASIC devices (Application Specific Integrated Circuits). PLDs can also be implemented in other ways, e.g., using fuse or antifuse technology.
Whatever type of architecture is used, PLDs generally include many programmable logic blocks of various types interconnected by a programmable interconnect structure. Other circuits included in the PLD might or might not be programmable. These additional circuits can include, for example, configuration logic and a clock distribution structure (clock tree).
FIG. 1
shows a typical PLD and the clock tree included in the PLD. The PLD includes a plurality of programmable logic blocks LB and an array or interconnect matrix (not shown) interconnecting the function blocks. In an FPGA, logic blocks LB correspond, for example, to IOBs or CLBs; in a CPLD, logic blocks LB correspond to function blocks or macrocells.
A PLD pad
101
is designated as the input clock pad, to which the system clock signal is supplied. The system clock signal is buffered (in inverting buffer
102
) to reduce the capacitance of the system clock node, then is delivered to an approximate center point CP of the PLD. From center point CP, the clock signal is radially distributed to multiplexers M
1
-M
4
and hence to inverting buffers B
1
-B
4
. The radial distribution equalizes the delay from the input clock pad
101
to the destination logic blocks LB.
The system clock signal is routed from center point CP to multiplexers M
1
-M
4
, which are individually controlled by configuration memory cells MC
1
-MC
4
to pass either the system clock signal or a power high signal VDD. Each inverting buffer B
1
-B
4
provides a selected signal to one quadrant of the PLD. Thus, if only a portion of the logic blocks are needed to implement a particular design, one or more quadrants can be left deliberately unused when logic is assigned to the logic blocks, and the corresponding multiplexer M
1
-M
4
can be configured such that the corresponding clock buffer B
1
-B
4
supplies the ground signal to the unused quadrant. In CMOS logic, power consumption is largely due to nodes changing state. Thus, grounding the clock signal for an entire quadrant of the device can potentially cut power usage of the PLD as a whole by as much as twenty-five percent.
FIG. 2
shows another prior art PLD, in which a further level of clock control is provided by including for each logic block a programmable clock buffer CB, interposed between inverting buffer B
1
-B
4
and the input clock terminal of the logic block. Programmable clock buffer CB typically has the ability to select either the true or the complement clock signal for the logic block. Lo et al., in U.S. Pat. No. 6,456,126 B1, describe several such clock buffers, as well as several clock buffers having the additional capability of adding a programmable clock doubler function.
The PLDs of
FIGS. 1 and 2
include programmable clock trees wherein the power consumption of the PLD can be reduced by disabling the clock signal for one or more quadrants of the device. However, this scheme is only effective if the design implemented in the PLD uses up to three-fourths of the PLD, which can require the purchase of a more expensive PLD than might otherwise be required. Further, all input and output pads for the design must then be mapped to portions of the PLD having an enabled clock signal, which can make board design more difficult. Therefore, it is desirable to provide PLDs having clock trees that offer alternative methods of reducing power consumption. It is further desirable to provide clock buffers offering programmable functions in addition to those described above.
SUMMARY OF THE INVENTION
The invention provides novel clock divider and digital frequency synthesizer (DFS) circuits that add little additional delay on the clock path. Each rising and falling edge of an input clock signal triggers a pulse from a pulse generator circuit. These pulses are passed to a control circuit. True and complement versions of the input clock signal are also provided to a multiplexer circuit. Under the direction of the control circuit, the multiplexer circuit passes selected rising edges of the true clock signal, and selected falling edges of the complement clock signal, to an output clock terminal of the clock divider circuit. When neither the true nor the complement clock signal is passed by the multiplexer, a keeper circuit retains the value already present at the output clock terminal.
According to one embodiment of the invention, every Nth rising edge on the true clock signal is passed to the output terminal, where N is an even integer. Every Nth falling edge on the complement clock signal is also passed to the output terminal. This embodiment provides a divide-by-N output signal. In one embodiment, the selected edges are separated by N/2 rising edges. Thus, this embodiment provides a duty-cycle-corrected output clock signal.
The clock divider circuit of the invention provides the capability to divide by any even integer, rather than being limited to powers of two as are many clock dividers. The delay through the clock divider circuit is the same, regardless of which even number is selected as the divisor.
In one embodiment of the invention, the control circuit is implemented as a counter followed by a decoder circuit. In other embodiments, the control circuit is a state machine having at least four states. In a first state, the state machine enables the “true” path through the multiplexer circuit and disables the “complement” path. In a second state, the state machine disables both paths through the multiplexer, and the next transition is to a third state. In the third state, the state machine enables the “complement” path through the multiplexer circuit and d
Cartier Lois D.
Le Dinh T.
Xilinx , Inc.
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