Multi-purpose cache memory selectively addressable either as a b

Details Multi-purpose cache memory selectively addressable either as a b Multi-purpose cache memory selectively addressable either as a b

1987-05-11

1992-10-13

Lee, Thomas C.

Boots, shoes, and leggings

395700, 3642802, 364280, 36424341, 364230, 364DIG1, G06F 1200

Patent

active

051558335

ABSTRACT:
In a master-slave multiprocessor (FIG. 1), a slave processor (110) includes a random access memory array (119) that serves at initialization time as the slave processor's boot memory and that serves during normal operation time as the slave processor's cache memory. A master processor (120) writes the slave processor's boot program into the memory array when the memory array is to serve as the boot memory, i.e., following system reset.

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