Multi-processor system for supporting multicasting communication

Electrical computers and digital processing systems: multicomput – Computer-to-computer data addressing

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Details

709213, 709216, G06F 1516

Patent

active

061015512

ABSTRACT:
A packet is held in a FIFO memory through a network. The packet includes a header and data. The header includes fields of a packet type, a data length, and a designation for a processor. The packet type field defines whether its packet is either a single-cast packet or a multi-cast packet and a designation method for a destination address. There are several methods for the destination address: first, a method using a message buffer in a memory, secondly, a method using a value of an address register previously set, and thirdly, a method designating as a destination address. The (original) entity of the address register may be reserved in the memory. In this case, different message buffers for every task identifier may also be reserved in the memory.

REFERENCES:
patent: 5437017 (1995-07-01), Moore et al.
patent: 5504872 (1996-04-01), Tanaka
patent: 5790804 (1998-08-01), Osborne

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