Patent
1994-11-10
1998-08-18
Sheikh, Ayaz R.
395553, 395726, G06F 1516
Patent
active
057969469
ABSTRACT:
Processors in a multi-processor system are synchronized with each other without repeated initializations of a shared region whose value is representative of the number of processors which have reached a synchronized condition. Each processor exclusively accesses the shared region to increment the value kept in the shared region, calculates a comparison value which is based on the value kept in the shared region and which is representative of whether all processors in the multi-processor system have reached the synchronized condition, and examines the comparison value to see if all processors in the multi-processor system have reached the synchronized condition. If so, a branch is made to a next process but, if not, the processor waits until all processors have reached the synchronized condition.
REFERENCES:
patent: 5127092 (1992-06-01), Gupta et al.
patent: 5363495 (1994-11-01), Fry et al.
patent: 5434995 (1995-07-01), Oberlin et al.
patent: 5448732 (1995-09-01), Matsumoto
patent: 5452101 (1995-09-01), Keith
patent: 5475856 (1995-12-01), Kogge
O'Keefe et al., "Hardware Barrier Synchronization: Static Barrier MIMD (SBM)", 1990 International Conference on Parallel Processing, vol. 1 (1990), pp. 35-42.
Etienne Ario
NEC Corporation
Sheikh Ayaz R.
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