Electrical computers and digital processing systems: processing – Processing architecture – Array processor
Reexamination Certificate
2007-04-10
2007-04-10
Dharia, Rupal (Department: 2153)
Electrical computers and digital processing systems: processing
Processing architecture
Array processor
C709S201000
Reexamination Certificate
active
10085132
ABSTRACT:
A multi-processor system apparatus allows a compiler to perform a static scheduling action easily and can conduct the transfer of data packets without collision in response to a common pattern of simultaneous access demands. Processor elements are interconnected by a multi-stage interconnection network having multiple stages. As each of switching elements in the multi-stage interconnection network is preliminarily subjected to the static scheduling action of a compiler. The multi-stage interconnection network is emulated without producing collision of data. When the transfer of packets is carried out in one clos network arrangement of the multi-stage interconnection network, the scheduling of switching elements SE0to SE3in the exchanger at Level 1 is determined so that a packet lost in the arbitration is transferred through the free port of any applicable one of the switching elements.
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Amano Hideharu
Morimura Tomohiro
Dharia Rupal
Reilly Sean
Semiconductor Technology Academic Research Center
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