Boots – shoes – and leggings
Patent
1987-08-31
1990-06-19
Eng, David Y.
Boots, shoes, and leggings
36492792, 36492793, 36492798, 36492711, 364935, 3649352, 3649354, 36493546, 3649328, G06F 300, G06F 1516, G06F 1300
Patent
active
049358944
ABSTRACT:
A multi-processor, multi-bus system comprises a host processor and a cluster controller coupled to a first type of bus; a local processor coupled to a second type of bus; and bus interface circuits coupled to the first and second bus types for selectively enabling the second bus to be coupled to the host processor, and for selectively enabling the first bus to be coupled to the local processor. Both bus types are asynchronous. Each bus interface circuit comprises a first-in-first-out (FIFO) register, interrupt logic, and transmitter/receiver logic. The pair of bus interface circuits together provide dual simplex data transfer between the local processor and the cluster controller which is directed by a parallel data ling (PDL) protocol. The protocol utilizes a 16-bit wide control word. The most significant bit 15, referred to as the command bit, is a "one" whenever bits 0-7 contain a command byte, while the command bit is "zero" whenever bits 0-7 contain a data byte. A logical unit number specified in bits 8-14 indicates to which of 128 possible logical devices the information transfer is destined.
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"CMOS Parallel First-In/First-Out FIFO 512.times.9 Bit & 1024.times.9 Bit", Military and Commercial Temperature Ranges, pp. 2-34-2-42.
Bruner Robert W.
Huey Christopher A.
Ternes Robert J.
Chan Emily Y.
Eng David Y.
Motorola Inc.
Nielsen Walter W.
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