Computer graphics processing and selective visual display system – Computer graphic processing system – Plural graphics processors
Reexamination Certificate
2002-05-01
2003-03-18
Tung, Kee M. (Department: 2671)
Computer graphics processing and selective visual display system
Computer graphic processing system
Plural graphics processors
C345S581000
Reexamination Certificate
active
06535216
ABSTRACT:
FIELD OF THE INVENTION
The invention generally relates to computer graphics processing and, more particularly, the invention relates to graphics accelerators having parallel processors.
BACKGROUND OF THE INVENTION
Graphics rendering devices commonly include parallel processors for improving processing speed. In some prior art systems, each parallel processor processes data for a relatively large preselected contiguous portion of a display device. For example, in a four parallel processor graphics accelerator, each processor may produce pixel data for one quadrant of the display device. Accordingly, when an image to be drawn is substantially within one of the quadrants of the display, only one processor is processing while the other processors remain relatively dormant. This can significantly slow system speed, thus decreasing system efficiency.
Other problems commonly arise in multi-parallel processor graphics accelerators such as, for example, graphics requests being processed out of a prescribed sequential order. When this happens, the processors often produce output pixel data that is out of sequence and thus, not an accurate depiction of the image being drawn. It therefore would be desirable to provide a parallel processing graphics accelerator that divides processing more evenly among the processors, while also maintaining the order of sequential graphics requests that ultimately are transformed into pixel data.
SUMMARY OF THE INVENTION
In accordance with one aspect of the invention, an apparatus for displaying a polygon on a horizontal scan display device having a plurality of pixels includes first and second rasterizers that each process respective first and second sets of pixels. Each set of pixels includes vertical stripes that are transverse to the horizontal scan of the display. To that end, the first rasterizer has an input for receiving polygon data relating to the polygon. The first rasterizer determines a first set of pixels that are to be lit for display of the polygon, and also determines display characteristics of the first set of pixels. In a similar manner, the second rasterizer also includes an input for receiving polygon data relating to the polygon. The second rasterizer similarly determines a second set of pixels that are to be lit for display of the polygon, and also determines display characteristics of the second set of pixels. The first and second sets of pixels have no common pixels and are vertical stripes of pixels on the display device that are transverse to the direction of the horizontal scan. In alternative embodiments, the display device has an arbitrary scan direction and the stripes are transverse to the arbitrary scan direction.
In preferred embodiments, the apparatus is a graphics accelerator having a first and second frame buffers, and first and second resolvers for transferring the display characteristics for the first and second sets of pixels into the first and second frame buffers, respectively. The first and second frame buffers may be formed on the same integrated circuit, or may be formed on different integrated circuits. In preferred embodiments, the first and second resolvers each include a plurality of resolvers. More particularly, the first resolver may include a first number of sub-resolvers, and the first frame buffer may be divided into a second number of frame buffer segments. Each sub-resolver may be assigned one frame buffer segment for exclusive use and thus, cannot transfer pixel data into other frame buffer segments. Each subresolver thus writes to its assigned frame buffer segment only.
In other embodiments, the first resolver includes first and second sub-resolvers. The first sub-resolver transfers display characteristics of a first sub-set of pixels to the first frame buffer while the second sub-resolver transfers display characteristics of a second sub-set of pixels to the first frame buffer. The pixels in the first and second sub-sets are members of the first set of pixels and each have pixels in the same vertical stripe.
In preferred embodiments, each vertical stripe includes a plurality of contiguous pixels. The first set of pixels includes a plurality of non-contiguous vertical stripes. The second set of pixels may include a plurality of non-contiguous vertical stripes. In some embodiments, each vertical stripe has a width of one pixel. Among other things, the display characteristics may include intensity information, color data, depth data, and transparency data.
The polygon data may include vertex data. In some embodiments, the vertex data define a triangle.
In accordance with another aspect of the invention, an apparatus for displaying an image (comprised of a plurality of polygons) on a display device having a plurality of pixels includes first and second gradient producing units that broadcast ordered sets of data in a preselected order to a bus. This preselected order maintains the order of the ordered sets of data.
Accordingly, in prefer-ed embodiments of the invention, the apparatus includes the first and second gradient producing units, and the bus coupled to each of the gradient producing units for receiving the data broadcast. To that end, the first gradient producing unit has an input for receiving a first ordered set of polygons, where each polygon in the first ordered set is received in a first order. In a similar manner, the second gradient producing unit has an input for receiving a second ordered set of polygons, where each polygon in the second ordered set is received in a second order. The first and second gradient producing units each having respective outputs for respectively providing gradient data for the first and second set of polygons. Each polygon in the first and second ordered sets are members of the set of polygons. The bus is coupled to both the outputs of the first and second gradient producing units, and at least one rasterizer that processes the plurality of polygons for display on the display device. The first gradient producing unit output broadcasts the gradient data for the first ordered set of polygons in the first order. In a similar manner, the second gradient producing unit output broadcasts the gradient data for the second ordered set of polygons in the second order. In preferred embodiments of the invention, the second gradient producing unit output broadcasts the gradient data for the second ordered set of polygons after the gradient data of each polygon in the first ordered set of polygons is broadcasted to the bus.
In other embodiments, the apparatus for displaying an image includes a first rasterizer having an input for receiving the first ordered set of polygons, and a second rasterizer that also has an input for receiving the first ordered set of polygons. The first rasterizer determines a first set of pixels that are to be lit for display of each polygon in the first set of ordered polygons. In a similar manner, the second rasterizer also determines a second set of pixels that are to be lit for display of each polygon in the first set of ordered polygons. The first set of pixels and second set of pixels have no common pixels, while the first set of pixels and second set of pixels each are vertical stripes of pixels on the display device. Each vertical stripe preferably includes a plurality of contiguous pixels. The first set of pixels preferably includes a plurality of non-contiguous vertical stripes, while the second set of pixels also includes a plurality of non-contiguous stripes.
The first gradient producing unit preferably produces gradient values for each polygon in the first ordered set of polygons. The polygons in the set preferably are triangles having vertices and data relating to the vertices. The apparatus for drawing an image preferably is a graphics accelerator that draws the image in three dimensions (i.e., “3D”).
In accordance with yet another aspect of the invention, a graphics accelerator for processing a graphics request stream includes first and second processors that each maintain control of a bus (at different times) until a flag is rec
Buckelew Matt E.
Deming James L.
Heinrich Steven J.
Johnson Timothy S.
Kirkland Dale L.
3DLabs Inc. Ltd.
Arnall Golden & Gregory LLP
Tung Kee M.
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