Multi-processor computer system having dual memory subsytems for

Details Multi-processor computer system having dual memory subsytems for Multi-processor computer system having dual memory subsytems for

1994-12-22

1997-06-03

Chan, Eddie P.

395474, 395308, G06F 1316, G06F 1336

Patent

active

056363613

ABSTRACT:
A multi-processor information handling system employs multiple multi-processor bus/memory subsystem groups wherein the processors may operate programs concurrently, and concurrent memory operations may be performed with the multiple memory subsystems via the associated multi-processor buses responsive to address location directors. The invention expands the system bandwidth and improves overall multi-processor information handling system performance.

REFERENCES:
patent: 5249283 (1993-09-01), Boland
patent: 5345566 (1994-09-01), Tanji et al.
patent: 5453957 (1995-09-01), Norris et al.
patent: 5497355 (1996-03-01), Mills et al.
patent: 5511224 (1996-04-01), Tran et al.
Frailong et al., "The Next-Generation SPARC Multiprocessing System Architecture", 1993, pp. 475-480, IEEE.

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