Multi-processor communications channel utilizing random access/s

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3642281, 3642306, 364244, 3642448, 364251, 364252, 3642548, 364260, 3642705, 3642706, 364DIG1, 3649314, 364940, 364950, 3649591, 364960, 364964, 3649646, 364965, 3649653, 3649659, 364DIG2, G06F 1300

Patent

active

051558076

ABSTRACT:
A system for transferring data between a pair of data processing units having system buses includes a plurality of memories in each of the data processing units; each memory having a random access portion and an associated sequential access portion; means for transferring data between each of the random access portions of each of the memories and its associated sequential access portion; and means connecting the sequential access portions of each of the memories in one of the data processing units to the sequential access portions of the other of said data processing units to permit data flow therebetween; the data flow between the sequential access portions of said memories occurring asynchronously of the remainder of the system so that the data processing units can utilize their system buses during such data flow.

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"Supplement to MOS Memory Data Book 1984", Texas Instruments, pp. 5-3 through 5-10.

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