Multi-processor architecture for a device

Details Multi-processor architecture for a device Multi-processor architecture for a device

2011-03-08

2011-03-08

Kumar, Pankaj (Department: 2467)

Multiplex communications

Pathfinding or routing

Combined circuit switching and packet switching

C370S401000, C710S306000, C710S312000

Reexamination Certificate

active

07903642

ABSTRACT:
Aspects of the invention provide apparatuses and methods for composing a device with different types of multi-processor subsystems based on expected latency times and processing bandwidths. An apparatus may include multi-processor subsystems with different performance characteristics that interact with each other through bridge modules and a central packet network. Different types of multi-processor subsystems include a multi-point bus network, a circuit-switched network, a packet-switch network, and a shared block device. The apparatus includes a plurality of components, where each component has at least one multi-processor subsystem. The apparatus may be partitioned into different detachable parts, which can operate in an independent manner. The detachable parts may be joined so that the detachable parts can interact. A service in one multi-processor subsystem may interact with another service in another multi-processor subsystem by sending messages between the services.

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