Telephonic communications – With usage measurement – Call traffic recording by computer or control processor
Patent
1985-05-14
1988-03-15
Schreyer, Stafford D.
Telephonic communications
With usage measurement
Call traffic recording by computer or control processor
379269, H04M 300
Patent
active
047318171
DESCRIPTION:
BRIEF SUMMARY
FIELD OF INVENTION
The present invention relates to a stored program controlled telecommunication establishment, the controlled and controlling parts of which comprise a plurality of establishment function blocks, which perform telephony functions and computer functions with the aid of instruction memory units and data memory units for storing establishment control information, and a plurality of processors which include at least one central processor, said function blocks and processors controlling in real time and in mutual co-operation the telephony traffic processed by the establishment with the aid of the stored control information, the co-operation functions containing determination of the consecutive order in which the establishment functional blocks perform their assigned functions.
BACKGROUND
A stored program controlled telecommunication establishment includes mutually co-acting telecommunication means for providing teleconnections, and a computer system for controlling the telephony traffic clearing process. As foundation stones the computer system includes an instruction memory and data memory for storing the necessary control information for controlling the telecommunication means and the computer system, as well as one or more processors controlling the execution of the control functions of the entire establishment in real time.
It was seen already during the sixties that many conventional telecommunication means can be implemented by a computer. According to state-of-the-art stored program controlling technique, function blocks are arranged which carry out assigned telecommunication functions and computer functions, their function execution being controlled by one or more processors. Real-time control requires, independent of the number of processors, function blocks for job-buffering and for job-priority, which determinate the consecutive order in which other function blocks carry out their assigned functions as efficiently as possible.
In the arrangement of a plurality of processors, processor load distribution is obtained with the aid of so-called "preprocessing" and "multiprocessing".
By preprocessing is meant that given regional control functions are carried out with the aid of regional processors and regional memories arranged in the associated function block, a central processor commanding the execution of the functions and receiving their result. The regional processors and central processor each control their given function clearings. A computer system with a constant distribution of control load and with the possibility of execution overlapping is obtained, but in principle a regional processor system is still a one-processor system, where the central processor controls function blocks provided with regional processors and where co-operation between the function blocks and the central processor requires well-defined interprocessor co-operation controlled by the central processor.
In multiprocessing at least two central processors are arranged, these together having access to the data memory of the establishment, and there is obtained a number of possibilities for computer configurations and control load distributions existing during operational periods. A processor redundancy is used that enables, without rigorous reconfiguration of the computer system, variation in real time of the rules according to which the control load is distributed to the central processors. The tasks of the processors are thus adjusted dynamically and optimally to the instantaneous telephony traffic clearing process.
It is known to combine preprocessing with multiprocessing and also to introduce regional processor redundancy.
The above mentioned advantages, i.e. function execution carried out in parallel due to constant or flexible processor load distribution, are obtained at the cost of the disadvantage that it is absolutely necessary to have interprocessor communication and processor co-operative functions, which constitute an extra computer load and which must be graded as inefficient in relation to t
REFERENCES:
patent: 4256926 (1981-03-01), Pitroda et al.
Avsan Oleg
Jonsson Bjorn E. R.
Schreyer Stafford D.
Telefonaktiebolget LM Ericsson
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