Multi-power semiconductor integrated circuit device

Details Multi-power semiconductor integrated circuit device Multi-power semiconductor integrated circuit device

2001-02-12

2004-07-27

Cunningham, Terry D. (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Synchronizing

C365S226000

Reexamination Certificate

active

06768354

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a multi-power semiconductor integrated circuit device and, more particularly, to a multi-power semiconductor integrated circuit device in which a logic circuit and a memory are integrated on the same semiconductor chip. More specifically, the present invention relates to a power supply structure of a system LSI in which a logic such as a processor and a DRAM (Dynamic Random Access Memory) are integrated on the same semiconductor chip.
2. Description of the Background Art
FIG. 16
is a diagram schematically showing a structure of a conventional general-purpose DRAM (Dynamic Random Access Memory). In
FIG. 16
, the conventional DRAM includes a memory cell array MA having memory cells arranged in matrix of rows and columns, sense amplifiers SA for sensing, amplifying and latching data of memory cells connected to a selected row of the memory cell array MA, a row decoder RD for selecting an addressed row of the memory cell array MA, a control circuit CTL for controlling internal operation of the DRAM, and an internal voltage generation circuit IVG receiving an external power supply voltage VDDH for generating internal (power supply) voltages VDDS, VPP and VDDP therefrom.
The internal voltage VDDS is applied to the sense amplifiers SA as an operation power supply voltage. By the power supply voltage for sense amplifiers (array power supply voltage) VDDS, a logical high or “H” level voltage level of storage data of a memory cell in the memory cell array MA is determined.
The internal voltage VPP is transmitted to a word line arranged corresponding to a selected row of the memory cell array MA through the row decoder RD. The voltage VPP is generated by boosting the external power supply voltage VDDH.
The internal voltage VDDP is applied to the control circuit CTL as an operation power supply voltage. The power supply voltages VDDS and VDDP are generated by down-converting the external power supply voltage VDDH.
General-purpose DRAM in general receives the single power supply voltage VDDH for an supplied external power supply and generates an internal voltage of a necessary voltage level internally to operate. In general, the voltage level of the external power supply voltage VDDH is determined by an external factor, a power supply voltage supplied to a system where the DRAM is used. The internal (power supply) voltages VDDS, VDDP and VPP have their voltage levels determined by a gate length following miniaturization of an internal transistor. In miniaturization, a gate length and a gate insulation film are proportionally reduced according to the scaling rule. Therefore, a breakdown voltage is determined by a gate length of a MOS (insulated gate type field effect) transistor and a voltage level of an internal voltage is determined accordingly. For example, when the external power supply voltage VDDH is 3.3 V, the boosted voltage VPP is 3.6 V, the sense amplifier power supply voltage (array power supply voltage) VDDS is 2.0 V, and the power supply voltage for a control circuit in peripheral circuitry (periphery power supply voltage) VDDP is 2.5 V.
In recent years, system LSIs have been widely used in which logic circuits and DRAMs having a large storage capacity are integrated on the same semiconductor substrate. In such system LSIs, transistors more scaled down than transistors in a DRAM part are used for components of a logic circuit part in order to improve performance of the logic circuit and increase an integration degree. Therefore, as a power supply voltage of the logic circuit part, a power supply voltage lower than that of the DRAM part is employed.
FIG. 17
is a diagram schematically showing a power supply structure of such a system LSI. In
FIG. 17
, the system LSI SLS includes a logic LG and a DRAM macro DM. The DRAM macro DM, similarly to the general-purpose DRAM shown in
FIG. 16
, includes a memory cell array MA, a row decoder RD, sense amplifiers SA and a control circuit CTL. For the control circuit CTL, a MOS transistor is used, which is the same in size (gate insulation film thickness) as that of a transistor used in the logic LG. In the DRAM macro DM, an internal voltage generation circuit IVGA is provided. The internal voltage generation circuit IVGA generates a sense amplifier power supply voltage VDDS and a word line driving boosted voltage VPP from an external power supply voltage VDDH. To the logic LG, a dedicated power supply voltage VDDL is applied externally. When the logic power supply voltage VDDL is generated by down-converting the external power supply voltage VDDH for DRAM, an ineffective power in a down-converting circuit is increased to increase power consumption. Therefore, the power supply voltage VDDL for the logic LG is applied from an external source. The external power supply voltage VDDL for logic is also applied to the control circuit CTL. Use of the same transistor (transistor having the gate insulation film being the same in thickness and material) as that of the logic LG in the control circuit CTL enables the control circuit CTL to operate at a high speed.
Therefore, for such a system LSI SLS as illustrated in
FIG. 17
, two power sources, the external power supply voltage VDDH for DRAM and the power supply voltage VDDL for logic, are used.
In row decoder RD as illustrated in
FIGS. 16 and 17
, a signal of the boosted voltage VPP level needs to be driven according to a signal having an amplitude of the power supply voltage VDDP or VDDL level, and level conversion of the input signal is required for the row decoder RD.
FIG. 18
is a diagram showing one example of a structure of a VDDL/VPP level conversion circuit. In
FIG. 18
, the VDDL/VPP level conversion circuit includes an inverter IV
1
receiving an input signal SigL whose amplitude is at a VDDL level, an inverter IV
2
receiving the output signal of the inverter IV
1
, an N channel MOS transistor NTR
1
responsive to the output signal of the inverter IV
1
for coupling a node ND
1
to a ground node, an N channel MOS transistor NTR
2
responsive to the output signal of the inverter IV
2
for coupling a node ND
2
to the ground node, a P channel MOS transistor PTR
1
responsive to the signal of the node ND
2
for coupling a boosted voltage node to the node ND
1
, a P channel MOS transistor PTR
2
responsive to the signal on the node ND
1
for coupling the boosted node to the node ND
2
, and an inverter IV
3
for inverting the signal on the node ND
2
to generate an output signal SigP having an amplitude of a boosted voltage VPP level. The inverters IV
1
and IV
2
receive a voltage VDDL (or VDDP) as one operation power supply voltage. The inverter IV
3
receives a boosted voltage VPP as one operation power supply voltage.
In the level conversion circuit shown in
FIG. 18
, when the input signal SigL is at a “H” level of the voltage VDDL level, the MOS transistor NTR
1
is turned off and the MOS transistor NTR
2
is turned on, and the node ND
2
is driven to a ground voltage level and the node ND
1
is driven to the boosted voltage VPP level. The output signal SigP accordingly attains an H level of the boosted voltage VPP level.
When the input signal SigL is at a logical low or “L” level, the MOS transistor NTR
1
is turned on and the MOS transistor NTR
2
is turned off, and the node ND
1
attains the ground voltage level and the node ND
2
attains the boosted voltage VPP level. The output signal SigP accordingly attains a “L” level of the ground voltage level.
In the general-purpose DRAM shown in
FIG. 16
with a single external power source only, the internal voltages VDDS, VPP and VDDP are generated according to the external power supply voltage VDDH. Therefore, since at the time of power-on, the boosted voltage VPP is generated following the external power supply voltage VDDH with substantially no delay, there barely arises a period in which a node of the level conversion circuit
32
is driven to an intermediate voltage level.
In a system LSI as illustrated in
FIG. 17
having two power sources, ho

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