Multi-port semiconductor memory device with reduced coupling noi

Details Multi-port semiconductor memory device with reduced coupling noi Multi-port semiconductor memory device with reduced coupling noi

1998-01-07

1999-03-23

Yoo, Do Hyun

Static information storage and retrieval

Interconnection arrangements

Magnetic

365 51, 365 63, 365156, 365190, 365207, 365214, G11C 700

Patent

active

058869190

ABSTRACT:
A semiconductor memory device has two complementary pairs of bit lines coupled to the same memory cells. According to a first aspect of the invention, the bit lines in one complementary pair cross over, so that each bit line in the first pair runs adjacent to one bit line in the second pair for one part of its length, and adjacent to the other bit line in the second pair for another part of its length. Coupling noise is thereby neutralized. Data-inverting circuitry is provided to compensate for the inversion of data that results from the cross-over of the bit lines. According to a second aspect of the invention, the two complementary pairs of bit lines are placed in separate interconnecting layers, to reduce coupling noise by reducing the capacitive coupling between the bit lines.

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