Multi-port memory device having variable port speeds

Details Multi-port memory device having variable port speeds Multi-port memory device having variable port speeds

2007-03-30

2009-12-29

Nguyen, Tuan T (Department: 2824)

Static information storage and retrieval

Addressing

Sync/clocking

C365S233100, C365S233120

Reexamination Certificate

active

07639561

ABSTRACT:
A multi-port memory device having two or more ports wherein each port may operate at a different speed. The multi-port memory device contains memory banks that may be accessed via the two or more ports. Two clock signals are applied to each port: a system clock and a port clock. The system clock is applied to port logic that interfaces with the memory banks so that the ports all operate at a common speed with respect to the memory banks. The port clock is applied to a clock divider circuit that is associated with each port. The port clock is divided to a desired frequency or kept at its original frequency. Such a configuration allows the ports to operate at different speeds that may be set on a port-by-port basis.

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First Examination Report as received in related European Patent Application No. EP07759902.5 on Feb. 26, 2009, (9 pages).
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