Multi-port memory as a frame buffer

Details Multi-port memory as a frame buffer Multi-port memory as a frame buffer

1989-10-31

1993-04-06

Lee, Thomas C.

Boots, shoes, and leggings

3649272, 3649397, 36496431, 364DIG2, 395425, 395725, G06F 314, G06F 1300

Patent

active

052010376

ABSTRACT:
A display system uses a dual-port memory having a random access memory part and a serial access memory part as a frame buffer. Display data is transferred from the random access memory part to the serial access memory part in response to a timing signal of the data transfer. Just prior to the timing signal, an access start disable signal is generated, which has an active period being equal to or longer than an access cycle time of drawing data. When the access start disable signal is active, a draw access from a central processing unit, etc. to the dual port memory becomes disable. Further, address bits for a column of the memory are detected to become all zero and a predetermined value, so that the timing of a real time data transfer and the access start disable signal for the real time data transfer can be generated.

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Eiichi Kumagai et al. "Dual-port Memory and Gate Arrays" Nikkei Electronics, No. 398, Jun. 30, 1986, pp. 1-14.

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