Coating apparatus – Gas or vapor deposition
Reexamination Certificate
1999-10-06
2001-10-02
Bueker, Richard (Department: 1763)
Coating apparatus
Gas or vapor deposition
Reexamination Certificate
active
06296710
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates to semiconductor processing and, more particularly, to a multi-port gas injector for a vertical furnace utilized for low-pressure chemical-vapor-deposition of silicon dioxide from a tetraethyl orthosilicate (“TEOS”) source.
2. Description of the Relevant Art
Fabrication of integrated circuits upon semiconductor substrates (“wafers”) involves numerous processing steps. For example, the fabrication of a metal-oxide-semiconductor (“MOS”) integrated circuit includes the formation of trench isolation structures within a semiconductor substrate to separate each MOS field-effect transistor (“MOSFET”) that will be made. The semiconductor substrate is typically doped with either n-type or p-type impurities. A gate dielectric, typically composed of silicon dioxide, is formed on the semiconductor substrate. For each MOSFET being made, a gate conductor is formed over the gate dielectric and a source and drain are formed by introducing dopant impurities into the semiconductor substrate. Conductive interconnect lines are then formed to connect the MOSFETs to each other and to the terminals of the completed integrated circuit. Modern high-density integrated circuits typically include multiple interconnect levels to provide all of the necessary connections. Multiple interconnect levels are stacked on top of each other with intervening dielectric levels providing electrical insulation between interconnect levels.
One common processing step in integrated circuit fabrication is chemical vapor deposition (“CVD”) that is utilized to deposit thin films on the upper surfaces of semiconductor substrates. The CVD process involves introducing reactant gases into a reaction chamber and then decomposing and reacting the gases at a heated surface of a semiconductor substrate to form a thin film. Typical films deposited by CVD include polysilicon, silicon dioxide, silicon nitride, and silicon oxynitride. For example, CVD may be used to deposit silicon dioxide to fill trench isolation structures, which may subsequently be polished by chemical-mechanical polishing to remove silicon dioxide external to the trenches, or to deposit polysilicon, which may be subsequently patterned to form gate electrodes.
A variety of different CVD techniques have been developed. All CVD techniques strive to optimize a variety of parameters including uniformity of film thickness, particulate generation, and throughput. Film thickness uniformity becomes increasingly important as the minimum feature size of devices formed on the semiconductor substrate continues to be reduced. Films of better thickness uniformity require less additional processing steps to planarize thereby reducing manufacturing costs. It is also desired to reduce the quantity of particles generated by CVD since such particles have the potential to destroy the integrated circuit being formed. Additionally, higher throughput decreases manufacturing costs by reducing the quantity of CVD reactors required to process a given number of wafers in a fixed period of time.
One popular form of CVD is low-pressure CVD (“LPCVD”) in which the pressure of the reactant gases is much less than atmospheric pressure. LPCVD is capable of producing films with good thickness uniformity. Since LPCVD operates at low pressure, gas-phase reactions of the reactant gases are reduced thereby reducing particulate formation. Since the rate at which a film is deposited by LPCVD tends to be limited by the reaction rate of reactant gases at the semiconductor surface (as opposed to being limited by the mass transfer rate of reactant gases to the semiconductor substrate surface), LPCVD reactors may be optimized to process large quantities of semiconductor substrates simultaneously.
In semiconductor fabrication, silicon dioxide is frequently deposited using LPCVD from a TEOS source.
FIG. 1
shows a side-view cross-sectional schematic of a vertical furnace that may be used for LPCVD of silicon dioxide using a TEOS source. An example of a vertical furnace is the Alpha-8S manufactured by Tokyo Electron Limited of Tokyo, Japan. Vertical furnace
10
holds a plurality of semiconductor substrates
12
within boat
14
. Boat
14
may hold greater than 150 semiconductor substrates. Boat
14
is arranged upon pedestal
22
that is adapted to rotate boat
14
during deposition of silicon dioxide. Tube
18
defines a reaction chamber and liner
16
is arranged between boat
14
and tube
18
. Boat
14
, liner
16
, tube
18
, and pedestal
22
are typically made of quartz. Thermal insulating cover
20
surrounds tube
18
and heating elements (not shown) on an inner surface of cover
20
provide heat to the interior of vertical furnace
10
. Liner
16
, tube
18
, cover
20
, and pedestal
22
are mounted on base
24
that is composed of a heat-resistant material such as stainless steel. Gas injectors
26
and
28
are connected to base
24
by feedthroughs
30
. Gas injectors
26
and
28
are adapted to introduce the reactant gases of TEOS and O
2
, respectively, within liner
16
. Gas injectors
26
and
28
are simple cylindrical tubes typically composed of quartz. Exhaust conduit
32
is adapted to evacuate tube
18
and to remove used reactant gases from tube
18
. Exhaust conduit
32
is typically connected to a vacuum pump and adjustment of the pumping speed of gases through exhaust conduit
32
allows the pressure within the reaction chamber to be set.
Deposition of silicon dioxide begins by placing a plurality of semiconductor substrates
12
into boat
14
and placing boat
14
within tube
18
. The interior of vertical furnace
10
is heated and tube
18
is evacuated through exhaust conduit
32
. While boat
14
and pedestal
22
rotate, TEOS and O
2
gases are introduced through gas injectors
26
and
28
. Liner
16
is used to contain the reactant gases in close proximity to semiconductor substrates
12
and also constrains the gas to flow up the vertical furnace to the top of tube
18
. Boat
14
has an open structure that allows the reactant gas to also flow over the surfaces of semiconductor substrates
12
. The TEOS gas thermally decomposes at the surfaces of semiconductor substrates
12
resulting in silicon dioxide being deposited on the surfaces of semiconductor substrates
12
. Once the gas reaches the top of tube
18
, it flows back down between liner
16
and tube
18
and subsequently exits through exhaust conduit
32
. Typical operating parameters include flow rates of 190 sccm of TEOS and 5 sccm of O
2
, a temperature in the reaction chamber of 680° C., and a pressure within the reaction chamber of 500 mTorr.
The thickness uniformity of silicon dioxide deposited with LPCVD from a TEOS source is dependent on the gas flow dynamics of the TEOS gas. The uniformity of the deposited silicon dioxide is also dependent upon the placement of semiconductor substrate
12
in boat
14
. For example,
FIGS. 2 and 3
show cross-sectional views of a silicon dioxide layer deposited on semiconductor substrates near the top and bottom of boat
14
, respectively. As can be seen, silicon dioxide layer
34
deposited on semiconductor substrate
12
typically exhibits a convex shape when deposited at the top of boat
14
(
FIG. 2
) and a concave shape when deposited at the bottom of boat
14
(FIG.
3
). At some point near the bottom of boat
14
, the shape of the deposited silicon dioxide layer
34
will make a transition between these two shapes.
Typically, the locations in boat
14
that exhibit the worst thickness uniformity are the top and very bottom positions. To help improve the overall uniformity of the deposited silicon dioxide, these positions are typically not used. If boat
14
can hold 170 wafers, only the middle 150 positions, for example, may be filled with product wafers (i.e., wafers on which functional circuits are being fabricated) during deposition. The top 10 positions and bottom 10 positions may then be filled with dummy wafers (i.e., wafers on which functional circuits are not being fabricated). The du
Allen Michael B.
Anundson Richard A.
Whigham William A.
Advanced Micro Devices , Inc.
Bueker Richard
Conley & Rose & Tayon P.C.
Daffer Kevin L.
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