Oscillators – Solid state active element oscillator – Transistors
Reexamination Certificate
2001-06-07
2004-02-10
Pascal, Robert (Department: 2817)
Oscillators
Solid state active element oscillator
Transistors
C331S057000, C331S175000, C331S167000
Reexamination Certificate
active
06690243
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates to electronic oscillators, and more particularly to a circuit and method for a multi-phase voltage controlled oscillator (VCO). Described herein are means for creating a VCO with multiple outputs, all operating at the same frequency, but each having a different phase relationship. For example, in an embodiment disclosed herein, the VCO generates four sine wave outputs at the same frequency and phase offsets of 0°, 90°, 180° and 270°. This configuration-is referred to as a “quadrature oscillator.” Oscillators having multiple phase outputs (i.e., multi-phase oscillators) are useful in applications such as clock recovery circuits incorporating phase-locked loops (PLLs) or delay-locked loops (DLLs). In some cases, it is possible to operate the PLL (or DLL) and the associated VCO at lower frequencies, if the VCO is capable of generating multiple output phases. This is advantageous, since the lower frequency circuitry is generally easier to design and cheaper to manufacture. The circuit and method disclosed herein support the generation of clock signals of four, eight, or arbitrarily many output phases, while overcoming many disadvantages inherent in conventional multi-phase oscillators.
2. Description of the Related Art
Modern high-speed data communications systems typically employ internal clock-referenced circuitry. It is often necessary for such circuitry to adjust its own operating frequency to match that of an incoming data stream. For example, a SONET bit stream is considered isonchronous with respect to the internal clock rate of a node receiving the stream. This means that, although their average clock rates are very close, the bit stream data rate is not actually synchronized with the circuitry in the SONET node. To achieve synchronization, the node adjusts its internal clock slightly to match the bit stream data rate. This is accomplished by a clock recovery circuit, which derives the necessary clock rate from the bit stream. Such circuits generally employ PLLs, or DLLs.
In its most basic form, a PLL consists of a variable oscillator combined with phase detection and control circuitry. The signal generated by the oscillator is continuously compared against an incoming clock signal, and the control circuitry adjusts the oscillator output frequency so the incoming clock signal and oscillator output are in phase. A PLL may be used, for example, to synchronize logic local to the PLL with the frequency and/or phase of an external clock signal, as may be required for data communications.
In contrast, a DLL contains a variable delay line combined with delay detection and control circuitry. A reference clock is supplied to both the variable delay in the DLL and to a clock distribution network in the external circuitry. The DLL control circuitry compares the clock signal fed back from the distribution network against the output of the variable delay, and then adjusts the variable delay until the two clocks match. In this manner, a DLL can compensate for the delay in the clock distribution network.
In clock recovery systems, or other high-speed applications employing PLLs or DLLs, it is often convenient or beneficial to use a multi-phase clock. For example, the phase detector in a typical clock recovery circuit requires both the rising and falling edges of an incoming clock (e.g., clock to be recovered) to achieve synchronization. Therefore, with a single-phase clock signal, the clock rate must equal the data rate of the incoming bit stream. If the clock generates multiple phases, however, the clock rate may be reduced, while still permitting the phase detector to accurately track the effective bit rate of the incoming data. SONET bit streams may have bit rates as high as 10 Gbps, or even 40 Gbps (e.g., SONET/SDH standard OC-192 specifies a transmission rate of 9953.28 Mbit/s, and OC-768 specifies a transmission rate of 39813.12 Mbit/s). Consequently, the PLL and other components of the clock recovery circuit are significantly simpler with a multi-phase oscillator than. with one providing only a single output phase. For the purposes of this specification, an oscillator with outputs at 0° and 180° (i.e., a differential output) will be considered a two-phase oscillator.
There is a simple way to derive a multi-phase oscillator from a single-phase oscillator. A single-phase oscillator can be run at a multiple of the desired frequency and its output divided down and separated into multiple phases using standard logic. For example, to create a 100 MHz four-phase oscillator, one could start with a single-phase oscillator running at 200 MHz. The 200 MHz output of this oscillator could be coupled to a divide-by-two counter. The two complementary outputs of each flip-flop would then yield a differential pair of 100 MHz waveforms (i.e., 180° out of phase with each other) that were 90° out of phase with the respective outputs of the other flip-flop.
Unfortunately, it is not always a simple matter to run the oscillator and the divider at twice (or more) the necessary frequency. Furthermore, the phase/frequency detectors used in some clock recovery circuits require as many as 4 or 8 phases. Using the above approach, it would be necessary to start with a oscillator running at 8 times the bit rate, which may be impractical, if the targeted bit rate is quite high. In such cases, there is no alternative but to create an oscillator that.directly generates the multi-phase signals.
There are a variety of ways to create a multi-phase oscillator without multiplying and thereafter dividing the oscillator output. A classic approach, known as a RC ring oscillator, consists of series-connected phase shift stages, in which the combined phase shift is sufficient to achieve oscillation at the desired operating frequency. For example, a quadrature RC ring oscillator can be formed by connecting four stages in series, each stage having a phase shift of 90° at the desired frequency. By connecting the inverted output of the fourth stage to the input of the first, an overall phase shift of 360° results. If there is enough gain, the RC ring oscillator will sustain oscillation. During oscillation, each stage of the RC ring oscillator produces an output signal at a frequency determined by the RC networks, with a phase angle that is a multiple of 90°. Although this technique is straightforward, it tends to be noisy and lacks sufficient frequency stability for many applications.
A better approach, the LC ring oscillator, uses both inductors and capacitors in the phase shift stages. (“LC” oscillators are so named because the traditional symbols for inductance and capacitance are L and C, respectively). Each LC combination has a characteristic resonant frequency. At the resonant frequency the impedance of the LC network becomes real (since, at resonance, the inductive and capacitive reactance become equal in magnitude and opposite in sign, and therefore, cancel). An LC ring oscillator will preferentially oscillate at the resonant frequency of the LC networks in its stages. The LC combination is often referred to as a “tank circuit”, and the resonant frequency is based on the component values in the tank:
f
R
=
1
2
π
LC
where f
R
is the resonant frequency (in Hertz), L is the inductance (in Henries), and C is the capacitance (in Farads). When operated at its natural resonant frequency, the frequency stability of a properly designed LC ring oscillator is inherently better than that of oscillators based on RC phase shift networks. This is because the rate of change of phase with respect to frequency is much greater for the LC tank circuit than for an RC circuit. In order to generate multiple output phases, however, LC ring oscillators are typically not operated at the exact resonant frequency, but are slightly “detuned.” As a result, their frequency stability is no better than that of an RC ring oscillator, and may limit their performance in high-speed clock recovery applications.
A further consideration with regard to multi-phase osci
Conley & Rose, P.C.
Cypress Semiconductor Corp.
Daffer Kevin L.
Glenn Kimberly E
Pascal Robert
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