Multi-phase programming of multi-level memory

Details Multi-phase programming of multi-level memory Multi-phase programming of multi-level memory

2008-11-24

2010-10-26

Mai, Son L (Department: 2827)

Static information storage and retrieval

Floating gate

Particular biasing

C365S185020, C365S185030, C365S185190

Reexamination Certificate

active

07821840

ABSTRACT:
Systems, methods, and devices that facilitate multi-phase programming of data in a memory component are presented. Received data is programmed to a memory using multiple programming phases based on a predefined program pattern. A program learn is performed by varying drain voltages, as desired, to facilitate determining respective drain voltages related to specified subgroups associated with respective data levels for a first programming phase. A first programming phase is performed using learned drain voltages as initial drain voltages where drain voltage levels are varied during each program pulse to facilitate programming memory cells to respective intrinsic verify voltage levels based on respective data levels. A second programming phase is performed using ending drain voltages from the first programming phase as initial drain voltages where gate voltage levels are varied during each program pulse to facilitate programming memory cells to respective final verify voltage levels based on respective data levels.

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