Miscellaneous active electrical nonlinear devices – circuits – and – Signal converting – shaping – or generating – Clock or pulse waveform generating
Reexamination Certificate
1999-11-16
2001-06-12
Wells, Kenneth B. (Department: 2816)
Miscellaneous active electrical nonlinear devices, circuits, and
Signal converting, shaping, or generating
Clock or pulse waveform generating
C327S294000
Reexamination Certificate
active
06246275
ABSTRACT:
RELATED APPLICATIONS AND PATENTS
U.S. patent application Ser. No. 09/089,099, entitled “Digital Programmable Clock Generator with Improved Accuracy,” filed on May 29, 1998, and assigned to the assignee of the present invention, herein incorporated by reference.
BACKGROUND OF THE INVENTION
This invention relates to a clocked comparator and to a programmable signal generator. More particularly this invention relates to an apparatus and method for a high frequency clocked comparator and to an apparatus for a multi-phase programmable signal generator.
The basic function of a comparator is to examine a pair of signals so as to generate a comparison signal having one of two states depending on which examined signal has the largest value. In a clocked comparator the comparison occurs generally within a single clock cycle of a clock signal. The clock signal in a clocked comparator is generally a high frequency signal. Because signal evaluation typically must be completed in the first half of the clock cycle, the signals to be examined must be stable during the interval of the comparison. In a typical clocked comparator where one of the signals to be examined is fixed and the other signal (hereinafter identified as a data signal) is compared to the fixed signal, the data signal must achieve a “steady-state” condition during the first half of the clock cycle so that the comparison can be made. As such, the “settling time” of the data signal is temporally limited by the duration of the first half of the clock cycle. Alternatively, the clock cycle may be extended so as to accommodate the “settling time” of the data signal within the first half of the extended clock cycle. As such, the typical clocked comparator must operate at a slower frequency. This limitation of the typical comparator circuit is overcome by the present invention. In this Specification the “settling time” of the data signal is defined as the temporal interval required for the data signal to achieve a “steady-state” condition.
A clock generator is generally a device which produces a timing signal within a temporal period bounded by a clock cycle and having a unique wave-form. The wave-form is repeated in subsequent clock cycles. It is desirable to employ a clock generator that is simple so that it can be integrated onto an application specific integrated circuit (ASIC) at low cost. It is also desirable for the clock generator to generate a plurality of timing signals wherein each timing signal is programmable. The present invention provides a multi-phase programmable clock generator that may be implemented on a single ASIC chip.
SUMMARY OF THE INVENTION
The present invention provides a high frequency clocked comparator having two modes of operation during each cycle of a plurality of system clock cycles, including a signal acquire mode during a portion of each of said system clock cycles, and has a decision mode during another portion of each of the system clock cycles. The high frequency clocked comparator comprises several components, including a holding capacitor, a capacitor transfer switch, a capacitor charge switch, a voltage reference, a comparator feedback switch, and a decision register. The holding capacitor is coupled to the negative signal line of the comparator. The capacitor transfer switch is coupled to the holding capacitor and coupled to ground, and is adapted to provide a reference to ground for the holding capacitor during the decision mode of operation. The capacitor charge switch is coupled to the holding capacitor and coupled to the data signal line for storing charge on the holding capacitor, and is adapted to be closed during the acquire mode of operation. The voltage reference is coupled to the positive signal line of the comparator and coupled to ground for generating a voltage reference signal. The comparator feedback switch is coupled to the comparator so as to provide feedback between the comparator decision line and the positive signal line of the comparator to enable said comparator to function as a high gain operational amplifier follower during the decision mode of operation and to enable said comparator to function as a comparator during the acquire mode of operation. The decision register is coupled to the comparator decision line of the comparator, and is adapted to latch the state of the decision signal generated by the comparator during the decision mode of operation.
The present invention also provides a method of comparing two signals in a high frequency clocked comparator, comprising the steps of: configuring the clocked comparator to operate in an acquire mode and subsequently in a decision mode within one clock cycle of the clocked comparator; generating a decision signal during the acquire mode which is the summation of the data signal minus the voltage reference signal, wherein the clocked comparator is adapted to operate as a high gain operational amplifier; generating a decision signal having one of two states based on voltage level of the data signal as compared to the voltage reference signal during the decision mode; and latching the decision signal during the decision mode. The method further comprises the step of making the status of said decision signal available to external circuitry during the subsequent clock cycle.
The present invention also provides a multi-phase programmable clock generator for generating a plurality of timing signals. Each clock generator comprises: a multiplexer coupled to a respective data select line, a respective data feedback line, and a respective data line, wherein the multiplexer is adapted to select between the respective data line and the respective data feedback line based on the status of the respective data select signal. A plurality of single bit registers, called a shift register, are serially coupled together and include a first register and a last register, wherein the first register is coupled to the multiplexer and the last register is coupled to the respective feedback line so that each bit of the data signal may be latched into each one of the single bit registers on a first-in-first-out basis. Once the shift register is loaded with the data signal the multiplexer causes the contents of the shift register to be cycled through the shift register so as to generate a programmable timing signal.
REFERENCES:
patent: 4377757 (1983-03-01), Konemann et al.
patent: 5987555 (1999-11-01), Alzien et al.
patent: 6040725 (2000-03-01), Lee et al.
Frank Paul Andrew
Harrison Daniel David
McGrath Donald Thomas
Wodnicki Robert Gideon
Breedlove Jill M.
General Electric Company
Nguyen Hiep
Stoner Douglas E.
Wells Kenneth B.
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