Miscellaneous active electrical nonlinear devices – circuits – and – Signal converting – shaping – or generating – Having specific delay in producing output waveform
Reexamination Certificate
2002-05-30
2003-12-09
Nguyen, Minh (Department: 2816)
Miscellaneous active electrical nonlinear devices, circuits, and
Signal converting, shaping, or generating
Having specific delay in producing output waveform
C327S170000, C327S295000, C365S233100
Reexamination Certificate
active
06661271
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to edge rate control circuits generally, and, more particularly, to a method and/or apparatus for controlling the edge rate of low voltage differential signals, particularly at high frequencies.
BACKGROUND OF THE INVENTION
Referring to
FIG. 1
, a circuit
10
is shown implementing a conventional edge rate control circuit. The edge rate control of the circuit
10
is achieved by adding N parallel switches driven by a multi-phase clock through flip flops. The timing between the first and last clock phase determines the edge rates of the transmitted differential waveforms. The flip flops are used to synchronize the timing between V+ and V− and can also be used to synchronize between two or more buffers.
Referring to
FIG. 2
, a circuit
30
is shown implementing a conventional multi-phase clock generation circuit. A number of clock signals Clock<
1
> to Clock<N> are shown generated by a number of delay elements. The circuit
30
can be used to generate the clock signals Clock<
1
> to Clock<N> for the circuit
10
. There is a practical limit to the maximum frequency of operation based on the delay time between the clock signals Clock<
1
> and Clock<N> due to the feedback to the input RB of the SR-latch.
A disadvantage of the circuit
30
is that the feedback to the latch has dependency on each delay element in the delay path. Before the next piece of data in the circuit can be processed, the SR-latch must be reset via the input RB. If the SR-latch is not reset via the input RB then the data can be lost at the output of the buffer across the terminator of the circuit
10
at higher frequencies but the amplitude can be maintained.
FIG. 3
shows a timing diagram of the circuit
30
of FIG.
2
. The data signal
11
is shown extending beyond the rising edge of the signal Clock<N> for proper operation.
It would be desirable to provide a method and/or architecture that may overcome SCSI cable induced effects by providing a controlled rise time and pre-compensation.
SUMMARY OF THE INVENTION
The present invention concerns an apparatus comprising a plurality of serially cascaded delay cells each configured to generate a phase of a multi-phase signal and an intermediate signal, where (i) each of the delay cells is generally configured to respond to a bias signal and one of the intermediate signals and (ii) a first of the delay cells is generally configured to respond to an input signal.
The objects, features and advantages of the present invention include providing a method and/or architecture for controlling the edge rate of low voltage signals that may (i) overcome SCSI cable induced effects, (ii) provide a controlled rise time and pre-compensation, (iii) increase the maximum operating frequency of a clock signal, (iv) reduce or eliminate delay cell interdependency, and/or (v) optimize driver circuit flip flop performance.
REFERENCES:
patent: 4985639 (1991-01-01), Renfrow et al.
patent: 5566129 (1996-10-01), Nakashima et al.
patent: 5694377 (1997-12-01), Kushnick
patent: 5781055 (1998-07-01), Bhagwan
patent: 6324125 (2001-11-01), Frankowsky et al.
Edson W. Porter et al., “Programmable Transmit SCSI Equalization”, U.S. Ser. No. 09/921,350, Filed Aug. 2, 2001.
Burdick Brian E.
Von Thun Matthew S.
Maiorana P.C. Christopher P.
Nguyen Minh
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