Multi-phase clock monitor circuit

Details Multi-phase clock monitor circuit Multi-phase clock monitor circuit

1977-07-11

1978-09-26

Zazworsky, John

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

307246, 307269, 328109, 328120, H03K 518, H03K 1900

Patent

active

041173481

ABSTRACT:
A test circuit to continuously monitor both narrow width (.phi..sub.1 and .phi..sub.3) and wide width (.phi..sub.1+2 and .phi..sub.3+4) multi-phase clocks for proper toggling or switching. If any one of the clocks fails to toggle (i.e. remains at a constant output voltage level) or if either of the .phi..sub.1 and .phi..sub.3 or .phi..sub.1+2 and .phi..sub.3+4 clocks are on at the same time, the circuit provides a corresponding output signal, which signal is indicative of a clock failure.

REFERENCES:
patent: 3577087 (1971-05-01), Martin et al.
D. J. Zimmerman, "Missing-Clock Detector", IBM Technical Disclosure Bulletin, vol. 19, No. 5, Oct. 1976, pp. 1905-1906.

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