Multi-phase clock generation circuit

Details Multi-phase clock generation circuit Multi-phase clock generation circuit

2005-01-18

2005-01-18

Callahan, Timothy P. (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Phase shift by less than period of input

C327S296000

Reexamination Certificate

active

06844765

ABSTRACT:
A multi-phase clock generation circuit includes a clock generation circuit, first frequency divider circuit, first clock selection circuit, second to nth frequency divider circuits, second to nth clock selection circuits, and clock selection control section. The clock generation circuit generates 2n(n is a positive integer) reference clock signals having the same frequency and different phases. The frequency divider circuit frequency-divides one of the reference clock signals by 2 to generate clock signals 180° out of phase with each other. The first clock selection circuit selects one of each of the clock signals and a corresponding reference clock signal and outputs the selected signals as clock pulses. Each of the second to nth frequency divider circuits frequency-divides a clock pulse to generate clock signals 180° out of phase with each other.

REFERENCES:
patent: 6260151 (2001-07-01), Omizo et al.
patent: 6618462 (2003-09-01), Ross et al.
patent: 6731317 (2004-05-01), Ema et al.
patent: 04029409 (1992-01-01), None
patent: 2001-318731 (2001-11-01), None

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