Multi-phase clock generation and synchronization

Details Multi-phase clock generation and synchronization Multi-phase clock generation and synchronization

2002-04-26

2003-10-14

Callahan, Timothy P. (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Clock or pulse waveform generating

C327S149000, C327S158000, C327S163000

Reexamination Certificate

active

06633190

ABSTRACT:

TECHNICAL FIELD
This invention relates to circuit design, and more particularly to the low-noise generation and synchronization of multiple phases of a reference clock.
BACKGROUND
A variety of devices, including, for example, circuit-level devices, integrated-circuit-level devices, board-level devices, and system-level devices, often need various phases of a reference clock. Known techniques for providing these phases include global generation and distribution, synchronization of locally generated phases using, for example, phase locked loops (“PLLs”) or delay locked loops (“DLLs”), and feedback-free architectures.


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Wu et al., A Low-Jitter Skew-Calibrated Multi-Phase Clock Generator for Time-Interleaved Applications, Feb. 2001, Digest of Technical Papers, ISSCC, IEEE International Solid-State Circuits Conference, pp. 396-397, 470.
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