Multi-path multiplier

Details Multi-path multiplier Multi-path multiplier

1991-07-02

1993-07-06

Nguyen, Long T.

Boots, shoes, and leggings

G06F 752

Patent

active

052260038

ABSTRACT:
A low-cost high-speed multiplier comprises a first register for holding a multiplier; a second register for holding a multiplicand; a partial product generator for scanning the multiplier held in the first register to generate three partial products of the multiplicand held in the second register; a 4-input adder for finding the sum of the three partial products and a fourth number; a shift register for holding and shifting the sum; and a unit for returning the shifted sum except a shifted-out portion of the sum to an input of the 4-input adder. This arrangement can process three partial products in one time of addition.

REFERENCES:
patent: 4597053 (1986-06-01), Chamberlin
patent: 4706211 (1987-11-01), Yamazaki et al.
patent: 4745570 (1988-05-01), Diedrich et al.
patent: 4769780 (1988-09-01), Chang
Masato Nagamatsu et al., A 15 NS 32.times.32-Bit CMOS Multiplier with an Improved Parallel Structure, "Proceedings of the IEEE 1989 Custom Integrated Circuits Conference", pp. 10.3.1-10.3.4.

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