Pulse or digital communications – Equalizers – Automatic
Reexamination Certificate
2007-03-20
2007-03-20
Corrielus, Jean B. (Department: 2611)
Pulse or digital communications
Equalizers
Automatic
C375S285000, C375S348000
Reexamination Certificate
active
10681444
ABSTRACT:
Various systems and methods providing high speed decoding, enhanced power reduction and clock domain partitioning for a multi-pair gigabit Ethernet transceiver are disclosed. ISI compensation is partitioned into two stages; a first stage compensates ISI components induced by characteristics of a transmitter's partial response pulse shaping filter in a demodulator, a second stage compensates ISI components induced by characteristics of a multi-pair transmission channel in a Viterbi decoder. High speed decoding is accomplished by reducing the DFE depth by providing an input signal from a multiple decision feedback equalizer to the Viterbi based on a tail value and a subset of coefficient values received from a unit depth decision-feedback equalizer. Power reduction is accomplished by adaptively truncating active taps in the NEXT, FEXT and echo cancellation filters, or by disabling decoder circuitry portions, as channel response characteristics allow. A receive clock signal is generated such that it is synchronous in frequency with analog sampling clock signals and has a particular phase offset with respect to one of the sampling clock signals. This phase offset is adjusted such that system performance degradation due to coupling of switching noise from the digital sections to the analog sections is substantially minimized.
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Abnous Arthur
Agazzi Oscar E.
Creigh John L.
Hatamian Mehdi
Kruse David E.
Corrielus Jean B.
McAndrews Held & Malloy Ltd.
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