Coded data generation or conversion – Sample and hold
Reexamination Certificate
2002-04-26
2003-05-27
Jeanpierre, Peguy (Department: 2819)
Coded data generation or conversion
Sample and hold
C341S144000
Reexamination Certificate
active
06570516
ABSTRACT:
BACKGROUND OF THE INVENTION
The invention relates to a sample and hold circuit architecture that reduces pedestal error, offset error, droop error, and linearity errors, and relates especially to a plurality of such sample and hold circuits having inputs multiplexed to the output of a single DAC or other analog signal source. The invention also relates to a plurality of such sample and hold circuits having outputs multiplexed to the input of a single ADC.
It is well known that a single DAC, multiple sample/hold conversion circuit can have a number of advantages, including reduced integrated circuit die size and cost, improved channel-to-channel matching, improved integrated circuit yield, and reduced component trimming time, testing time, and cost. Despite these advantages of single DAC, multiple sample/hold conversion circuit, performance limitations on the capabilities of known sample/hold circuits have prevented more widespread use thereof. Specifically, known sample/hold circuits are subject to switching transient errors, pedestal errors, offset errors, and droop errors totaling approximately 50 millivolts, which limits the use of such known sample/hold circuits in single DAC, multiple sample/hold circuits to approximately 10 bit accuracy. Also, hold times of only a few microseconds are typical for known sample/hold circuits, and such short hold times necessitate use of high speed DAC for a single DAC, multiple sample/hold conversion circuit applications. The short hold times also necessitate a high refresh rate, which greatly increases power consumption, and also limits the number of sample/hold outputs that can be provided for the single high-speed DAC. Furthermore, the required high refresh rate greatly increases the number of transient impulses that appear at the sample/hold outputs per unit of time, and this increases the amount of switching noise and necessitates more complex filtering of the sample/hold outputs.
FIG. 1
illustrates what is believed to the closest prior art. Referring to
FIG. 1
, a single DAC, multiple sample/hold conversion circuit
1
includes a DAC 8228 digital-to-analog converter
2
(available from Analog Devices Inc.) having its output coupled to the input of an SMP08 circuit
3
(also available from Analog Devices Inc.) including multiple sample/hold circuits. Each of the eight sample/hold circuits in block
3
includes a switch
6
, a hold capacitor
8
, and an output amplifier
7
. Typically, one terminal of the switch
6
is connected to the (+) input of the operational amplifier
7
and to one terminal of a hold capacitor
8
. The other terminal of each switch
6
is connected to the output
5
of DAC
2
. An address decoder
4
controls which one of switches
6
-
1
,
2
. . .
8
is closed to charge the corresponding hold capacitor
8
-
1
,
2
. . .
8
to the output voltage of DAC
2
. The digital inputs of DAC
2
can receive digital input signals from any of a number of sources, and a corresponding address is applied to the input of address decoder circuit
4
to determine which sample/hold circuit in block
3
samples and stores the analog output into which the present digital input is converted. The output of each amplifier
7
provided as feedback to the (−) input of that amplifier to thereby configure the amplifier as a unity gain buffer.
The prior art single DAC, multiple sample/hold conversion circuit
1
of
FIG. 1
has several shortcomings. One is that there is no cancellation of pedestal errors which appear as an offset of the output voltage due to switching charge that is distributed onto the hold capacitor
8
of a sample/hold circuit when its input switch
6
is opened. Another shortcoming is that charge on the hold capacitor
8
is slowly discharged through parasitic leakage paths during the hold mode of each sample/hold circuit, causing “droop” of the output voltages (on conductors
9
-
1
,
2
. . .
8
) of the sample/hold circuit
3
during their respective hold modes. A third shortcoming of the prior art single DAC, multiple sample/hold circuit
1
of
FIG. 1
is that there is no mechanism for reducing linearity errors due to non-linearity of the output amplifier of the sample/hold circuit. Note that in the prior art sample/hold circuits the settling time and accuracy are limited by the amount of time required to fully charge the hold capacitor, and the voltage drop across the sampling switch has fallen to zero by the time the hold capacitor is fully charged. In the prior art sample/hold circuits, errors related to offset, linearity, and input common mode of the op-amp are translated directly to the output of the sample/hold circuit.
Another shortcoming of the prior art single DAC, multiple sample/hold conversion circuit of
FIG. 1
is that channel-to-channel crosstalk and hold time reduction result from the large range of signals that appear at the DAC output
5
in FIG.
1
and at the input of each sample/hold “channel” during its hold mode while other digital input signals are converted by DAC
2
during the acquire mode of the other channels. For example, sample/hold output
9
-
1
can be “programmed” to be +2.5 volts by a particular digital input converted by DAC
2
such that hold capacitor
8
-
1
is charged to +2.5 volts, and then sampling switch
6
-
1
is turned off. Sample/hold output
9
-
2
then is programmed to be −2.5 volts by another digital input digitized by DAC
2
such that hold capacitor
8
-
2
is charged to −2.5 volts and sampling switch
6
-
2
is turned off. While the analog value for the second channel including sample/hold output
9
-
2
is being “acquired”, i.e., is being sampled and held, sampling switch
6
-
1
has a voltage of +5 volts across it, which causes a significant corresponding leakage current that reduces the charge on hold capacitor
8
-
1
, contributing to the voltage droop of sample/hold output
9
-
1
in the positive direction during the time that the analog value to be output on conductors
9
-
2
is being acquired. Thus, opposite polarities of the two sample/hold output voltages result in opposite polarity output voltage droop contributions, and each sample/hold output voltage is affected by the values of the other sample/hold outputs in a sort of pseudo-random way. Therefore, the output voltage droop of each sample/hold circuit during its hold mode is unpredictable and its slope varies depending on the values and acquisition timing of the other sample/hold outputs.
Thus, there is an unmet need for an improved sample and hold circuit architecture that provides reduced pedestal error, offset error, droop error, and linearity error and does not exhibit channel-to-channel interaction.
There also is an unmet need for an improved sample and hold circuit architecture which provides reduced pedestal error, offset error, droop error, and linearity error and does not exhibit channel-to-channel interaction in a single DAC, multiple sample/hold conversion circuit including a plurality of such sample and hold circuits having inputs multiplexed to the output of a single DAC.
There also is an unmet need for an improved sample and hold circuit architecture which provides reduced pedestal error, offset error, droop error, and linearity error and does not exhibit channel-to-channel interaction in a single DAC, multiple sample/hold conversion circuit including a plurality of such sample and hold circuits having inputs multiplexed to the output of a single DAC and also provides rejection of various common-mode noise signals.
There also is an unmet need for an improved sample and hold circuit architecture which provides reduced pedestal error, offset error, droop error, and linearity error in a single ADC, multiple sample/hold conversion circuit including a plurality of such sample and hold circuits having outputs multiplexed to the input of a single ADC.
SUMMARY OF THE INVENTION
Accordingly, it is an object of the invention to provide an improved sample and hold circuit architecture which provides reduced pedestal error, offset error, droop error, and l
Brady W. James
Jeanpierre Peguy
Swayze, Jr. W. Daniel
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