Electrical computers and digital processing systems: multicomput – Computer-to-computer protocol implementing – Computer-to-computer data transfer regulating
Reexamination Certificate
2005-01-25
2005-01-25
Knight, Anthony (Department: 2121)
Electrical computers and digital processing systems: multicomput
Computer-to-computer protocol implementing
Computer-to-computer data transfer regulating
C709S243000, C710S107000
Reexamination Certificate
active
06848003
ABSTRACT:
A data processing system includes a plurality of nodes, which each contain at least one agent and each have an associated node identifier, and memory distributed among the plurality of nodes. The data processing system further includes an interconnect containing a segmented data channel, where each node contains a segment of the segmented data channel and each segment is coupled to at least one other segment by destination logic. In response to snooping a write request of a master agent on the interconnect, a target agent that will service the write request places its node identifier in a snoop response. When the master agent receives the combined response, which contains the node identifier of the target agent, the master agent issues on the segmented data channel a write data transaction specifying the node identifier of the target agent as a destination identifier. In response to receipt of the write data transaction, the destination logic transmits the write data transaction to a next segment only if the destination identifier does not match a node identifier associated with a node containing a current segment.
REFERENCES:
patent: 3766526 (1973-10-01), Buchanan
patent: 4905145 (1990-02-01), Sauber
patent: 5032985 (1991-07-01), Curran et al.
patent: 5081623 (1992-01-01), Ainscow
patent: 5179715 (1993-01-01), Andoh et al.
patent: 5327570 (1994-07-01), Foster et al.
patent: 5488694 (1996-01-01), McKee et al.
patent: 5579480 (1996-11-01), Cidon et al.
patent: 5588122 (1996-12-01), Garcia
patent: 5592622 (1997-01-01), Isfeld et al.
patent: 5623628 (1997-04-01), Brayton et al.
patent: 5659759 (1997-08-01), Yamadia
patent: 5682516 (1997-10-01), Sarangdhar et al.
patent: 5684961 (1997-11-01), Cidon et al.
patent: 5715428 (1998-02-01), Wang et al.
patent: 5734922 (1998-03-01), Hagersten et al.
patent: 5787468 (1998-07-01), Clark
patent: 5852716 (1998-12-01), Hagersten
patent: 5860109 (1999-01-01), Hagersten et al.
patent: 5881312 (1999-03-01), Dulong
patent: 5884046 (1999-03-01), Antonov
patent: 5887138 (1999-03-01), Hagersten et al.
patent: 5895484 (1999-04-01), Arimilli et al.
patent: 5937167 (1999-08-01), Arimilli et al.
patent: 5938765 (1999-08-01), Dove et al.
patent: 5958011 (1999-09-01), Arimilli et al.
patent: 5983259 (1999-11-01), Campbell et al.
patent: 5983301 (1999-11-01), Baker et al.
patent: 6006286 (1999-12-01), Baker et al.
patent: 6009456 (1999-12-01), Frew et al.
patent: 6011777 (2000-01-01), Kunzinger
patent: 6112283 (2000-08-01), Neiger et al.
patent: 6148327 (2000-11-01), Whitebread et al.
patent: 6161189 (2000-12-01), Arimilli et al.
patent: 6181262 (2001-01-01), Bennett
patent: 6219741 (2001-04-01), Pawlowski et al.
patent: 6333938 (2001-12-01), Baker
patent: 6343347 (2002-01-01), Arimilli et al.
patent: 6345371 (2002-02-01), Lam
patent: 6421775 (2002-07-01), Brock et al.
patent: 6487628 (2002-11-01), Duong et al.
patent: 6519649 (2003-02-01), Arimilli et al.
patent: 6519665 (2003-02-01), Arimilli et al.
patent: 6591307 (2003-07-01), Arimilli et al.
patent: 6671712 (2003-12-01), Arimilli et al.
Farrens et al., Workload and Implementation Considerations for Dynamic Base Register Caching, Proceedings of the 24th Annual International Symposium on Microarchitecture, pp. 62-68, Nov. 1991.*
Cho et al., Removing Timing Constraints of Snooping in a Bus-Based COMA Multiprocessor, International Conference on Parallel and Distributed Computing and Systems, Oct. 1996.*
Preiss et al., A Cache-based Message Passing Scheme for a Shared-bus, The 15th Annual International Symposium on Computer Architecture, pp. 358-364, Jun. 1988.*
Park et al., Address Compression Through Base Register Caching, Proceedings of the 23rd Annual Workshop and Symposium on Microprogramming and Microarchitecture, pp. 193-199, 1990.
Arimilli Ravi Kumar
Fields, Jr. James Stephen
Guthrie Guy Lynn
Joyner Jody Bern
Lewis Jerry Don
Booker Kelvin
Dillon & Yudell LLP
International Business Machines - Corporation
Knight Anthony
Salys Casimer K.
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