Electrical pulse counters – pulse dividers – or shift registers: c – Systems – Pulse multiplication or division
Reexamination Certificate
2002-07-31
2003-09-02
Wambach, Margaret R. (Department: 2816)
Electrical pulse counters, pulse dividers, or shift registers: c
Systems
Pulse multiplication or division
Reexamination Certificate
active
06614870
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention pertains to the art of frequency dividers. More particularly, it pertains to multi-modulus prescalers.
2. Art Background
There are many methods employed to generate a signal at a specified frequency. Within the field of frequency synthesis a circuit function known as a frequency divider is often used. The output of a frequency divider is less than its input frequency by some factor N. The divider is typically a digital circuit and the input and output waveforms are pulse trains at frequencies of Fc and Fc/N respectively. The modulus of this divider is ‘N.’
It is often desirable to have a frequency divider which is not constrained to a single divide ratio, N, for example a divider which can divide by any number between 50 and 100. Creating such a divider from combinatorial logic and flip-flops is difficult. A more elegant technique involves the use of a multi-modulus prescaler.
Frequency dividers are widely employed in Phase Locked Loops (PLLs). PLLs are well known to the art. In general, the signal from a high frequency oscillator is divided down and compared to a lower frequency reference signal. The error signal from this comparison is filtered and used as a control signal to alter the frequency of the high frequency oscillator. Thus the PLL locks the fluctuations of a noisy high frequency oscillator to those of a quiet reference signal. This is accomplished in part by using a frequency divider (called an N-divider) to divide down the high frequency oscillator by some value ‘N’ and then comparing this divided down signal to that of the reference signal. The PLL output frequency is ‘N’ times the reference frequency.
Multi-modulus prescalers are often employed in frequency dividers. Dual modulus prescalers divide by two factors, for example, ¾. Other multi-modulus prescalers are capable of more divisors, such as 8/9/12/13 or 16/17/20/21. The prescaler modulus is selected by a prescaler control circuit. The prescaler control circuit is programmed with the desired divide number, controls the modulus of the prescaler as a function of time, and produces an output pulse when the desired count is obtained. This output pulse is often called ‘terminal count’.
Many applications are concerned with phase noise and want the prescaler based N-divider to have the lowest possible phase noise. One source of phase noise is jitter in the active edge of the prescaler's terminal count pulse. This jitter is a result of signal-to-noise ratios and switching speed limitations within the prescaler control circuit and the prescaler.
What is needed is a way to reduce jitter and its resultant phase noise in prescaler based N-dividers.
SUMMARY OF THE INVENTION
Jitter is reduced in a multi-modulus prescaler N-divider by providing the prescaler with a terminal count request input, which when set causes the prescaler to produce an output pulse with edges synchronous with the input clock. The prescaler is driven by a control circuit which produces a terminal count request output which enables the prescaler to generate a terminal count output pulse whose active edge, irrespective of the divide ratio, is always a fixed number of input clock cycles before or after the end of the prescaler control cycle.
REFERENCES:
patent: 6501815 (2002-12-01), Stansell
patent: 6501816 (2002-12-01), Kouznetsov
Agilent Technologie,s Inc.
Martin Robert T.
Wambach Margaret R.
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