Oscillators – Automatic frequency stabilization using a phase or frequency... – Tuning compensation
Reexamination Certificate
2001-10-31
2003-05-06
Mis, David C. (Department: 2817)
Oscillators
Automatic frequency stabilization using a phase or frequency...
Tuning compensation
C331S00100A, C331S025000, C327S117000, C327S156000, C327S159000, C327S115000
Reexamination Certificate
active
06559726
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to a method and/or architecture for implementing programmable frequency modulation generally and, more particularly, to a method and/or architecture for implementing a multi-modulus counter in modulated frequency synthesis.
BACKGROUND OF THE INVENTION
Referring to
FIG. 1
, a block diagram of a circuit
10
is shown. The circuit
10
is a conventional modulated frequency synthesizer. The conventional approach employs a loadable counter
12
and an adder
14
in a feedback path of a phase-locked loop (PLL)
16
configured for frequency synthesis. A sum output of the adder
14
is loaded into the counter.
12
. The first addend is a base PLL feedback divisor value PB and the second addend is an offset from the base PLL feedback divisor value PO. The offset value PO can be provided from a lookup table
18
. The offset value PO can be any integer within the bounds of the adder
14
and counter
12
. The total feedback divisor PT is given by the equation PT=PB+PO. The adder
14
is used when the offset values PO are small compared to the base feedback divisor value PB. Supplying an offset instead of a full feedback divisor value reduces the size of the lookup table
18
.
Referring to
FIG. 2
, a block diagram of a circuit
20
is shown. The circuit
20
is similar to the circuit
10
except that a high speed PLL
16
′ is employed. The loadable counter
12
can be unable to operate at the speed of a voltage controlled oscillator (VCO) of the PLL
16
′. To allow the loadable counter
12
to operate at a lower speed than the PLL
16
′, the loadable counter
12
can be preceded by a prescaler
22
. The prescaler
22
can be implemented as a fixed divide-by-N circuit, where N is any integer greater than or equal to 2. Because the prescaler
22
precedes the loadable counter
12
, the prescaler
22
multiplies the total feedback divisor, resulting in a total feedback divisor equation of PT=N*(PB+PO), or PT=(N*PB)+(N*PO). Because the offset value PO is multiplied by the prescaler value N, the frequency resolution between adjacent PLL feedback divisor values is reduced. Reducing the frequency resolution makes frequency modulation synthesis with the circuit
20
more sensitive to PLL loop gain, hindering performance and resulting in more variation across process and environmental conditions.
SUMMARY OF THE INVENTION
The present invention concerns an apparatus comprising a first circuit and a second circuit. The first circuit may be configured to generate an output signal in response to a reference input and a feedback signal. The second circuit may be configured to generate the feedback signal according to a plurality of moduli in response to the output signal, a first control signal and a second control signal. The frequency of the output signal may be modulated in response to the second control signal.
The objects, features and advantages of the present invention include providing a method and/or architecture for implementing a multi-modulus counter in a modulated frequency synthesizer that may (i) use a multi-modulus counter in place of a fixed prescaler, a loadable counter and an adder to achieve the synthesis of frequency modulation, (ii) use a multi-modulus counter to synthesize a modulation profile, and/or (iii) provide spread spectrum modulated frequency synthesis or clocking.
REFERENCES:
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patent: 4864643 (1989-09-01), French et al.
patent: 4935944 (1990-06-01), Everett
patent: 5084907 (1992-01-01), Maemura
patent: 5172400 (1992-12-01), Maemura
patent: 5559502 (1996-09-01), Schutte
patent: 5689196 (1997-11-01), Schutte
patent: 5867068 (1999-02-01), Keating
patent: 6163181 (2000-12-01), Nishiyama
patent: WO 96/17305 (1996-06-01), None
patent: WO 98/34376 (1998-08-01), None
patent: WO 99/09712 (1999-02-01), None
Cypress CY24131, “Display Panel Spread Spectrum Clock Generator”, Dec. 2000, pp. 1-4.
Galen E. Stansell, “Loadable Divide-By-N With Fixed Duty Cycle”, U.S. Ser. No. 09/607,697, filed Jun. 30, 2000.
Cypress Semiconductor Corp.
Maiorana P.C. Christopher P.
Mis David C.
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