Static information storage and retrieval – Addressing – Sync/clocking
Reexamination Certificate
2006-06-06
2006-06-06
Nguyen, Tuan T. (Department: 2824)
Static information storage and retrieval
Addressing
Sync/clocking
C365S201000, C365S194000
Reexamination Certificate
active
07057967
ABSTRACT:
A synchronous semiconductor memory device is operable in a normal mode and an alternative mode. The semiconductor device has a command bus for receiving a plurality of synchronously captured input signals, and a plurality of asynchronous input terminals for receiving a plurality of asynchronous input signals. The device further has a clock input for receiving an external clock signal thereon, with the device being specified by the manufacturer to be operated in the normal mode using an external clock signal having a frequency no less than a predetermined minimum frequency. An internal delay locked loop (DLL) clocking circuit is coupled to the clock input terminal and is responsive in normal operating mode to be responsive to the external clock signal to generate at least one internal clock signal. control circuitry in the device is responsive to a predetermined sequence of asynchronous signals applied to the device's asynchronous input terminals to place the device in an alternative mode of operation in which the internal clocking circuit is disabled, such that the device may be operated in the alternative mode using an external clock signal having a frequency less than the predetermined minimum frequency. The alternative mode of operation facilitates testing of the device at a speed less than the minimum frequency specified for the normal mode of operation.
REFERENCES:
patent: 5384737 (1995-01-01), Childs et al.
patent: 5548560 (1996-08-01), Stephens, Jr. et al.
patent: 5666321 (1997-09-01), Schaefer
patent: 5796673 (1998-08-01), Foss et al.
patent: 5875153 (1999-02-01), Hii et al.
patent: 5920518 (1999-07-01), Harrison et al.
patent: 5995424 (1999-11-01), Lawrence et al.
patent: 6026465 (2000-02-01), Mills et al.
patent: 6130856 (2000-10-01), McLaury
patent: 6144598 (2000-11-01), Cooper et al.
patent: 6154418 (2000-11-01), Li
patent: 6201424 (2001-03-01), Harrison
patent: 6205514 (2001-03-01), Pawlowski
patent: 6208571 (2001-03-01), Ikeda et al.
patent: 6215709 (2001-04-01), Wright et al.
patent: 6266294 (2001-07-01), Yada et al.
patent: 6301190 (2001-10-01), Tsujino et al.
patent: 6333896 (2001-12-01), Lee
patent: 6335902 (2002-01-01), Nakaoka
patent: 6400643 (2002-06-01), Setogawa
patent: 6434083 (2002-08-01), Lim
patent: 6525989 (2003-02-01), Mizugaki et al.
patent: 6678205 (2004-01-01), Johnson et al.
patent: 2001/0019284 (2001-09-01), Buck
Janzen Jeffrey W.
Johnson Brian
Keeth Brent
Manning Troy A.
Martin Chris G.
Nguyen N
Nguyen Tuan T.
Wong, Cabello, Lutsch, Rutherford & Brucculeri
LandOfFree
Multi-mode synchronous memory device and methods of... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Multi-mode synchronous memory device and methods of..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Multi-mode synchronous memory device and methods of... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3630599