Static information storage and retrieval – Addressing – Sync/clocking
Reexamination Certificate
2001-12-26
2004-01-13
Nguyen, Van Thu (Department: 2824)
Static information storage and retrieval
Addressing
Sync/clocking
C365S194000, C365S230010, C327S269000, C327S141000, C327S155000
Reexamination Certificate
active
06678205
ABSTRACT:
FIELD OF THE INVENTION
This invention relates generally to semiconductor devices, and more particularly relates to synchronous semiconductor devices, i.e., semiconductor devices whose operation is coordinated by an externally-applied oscillating clock signal.
BACKGROUND OF THE INVENTION
The field of semiconductor devices, including microprocessors, memory devices, digital signal processors, and the like, is enormously active and rapidly developing. Various categories and sub-categories of semiconductor devices are known and commercially available. The ever-increasing popularity and ubiquity of computers and computer-based devices, both in the consumer and industrial realms, is such that the demand for semiconductor devices of a variety of different types will continue to grow for the foreseeable future.
As a general proposition, semiconductor devices can be classified into one of two broad categories: synchronous and asynchronous. A synchronous semiconductor device is one whose operation is coordinated by or synchronized with a (typically) externally-applied clock signal; whereas an asynchronous device requires no clock signal.
One of the more common categories of semiconductor memory devices used today is the dynamic random access memory, or DRAM. Among the desirable characteristics of any DRAM are a high storage capacity per unit area of semiconductor die area, fast access speeds, low power consumption, and low cost.
One approach that has been used to optimize the desirable properties of DRAM has been to design such devices such that they are accessible synchronously. A synchronous DRAM typically requires an externally-applied clocking signal, as well as other externally-applied control signals whose timing must bear certain predetermined relationships with the clock signal. Likewise, digital data is read from and written to a synchronous memory device in a synchronous relationship to the externally-applied clock signal. Synchronous DRAM technologies have been under development for many years, and synchronous DRAM (frequently referred to as “SDRAM”) is used in a broad spectrum of commercial and industrial applications, including the personal computer industry.
Those of ordinary skill in the art will appreciate that, as the storage capacity of SDRAMs is increased, so too does the die size of the semiconductor substrate usually increase (notwithstanding concurrent improvements in semiconductor processing technologies allowing for higher-density memory storage per unit area). It is also recognized that as the substrate size increases, other factors affecting the overall synchronization of the electrical signals propagating throughout the substrate also come into play. Issues such as capacitive coupling, impedance loading, processing variation and the like can make it challenging to ensure that the interrelationship between the timing of separate signals conducted along and within the substrate remains synchronized. As the processing speed of a semiconductor device increases, such synchronization issues (sometimes referred to generally as “skew”) can become more and more critical. Timing differentials on the order of picoseconds can become determinative of whether a device will operate reliably and properly.
In typical implementations, the external clock signal CLK comprises a simple, periodic “square” wave, such as shown in
FIG. 3
a
, oscillating with reasonably uniform periodicity between a logical high voltage level (for example, 3.3 V) and a logical low level (typically 0 V) with a duty cycle of 50% (meaning that the signal is at a logical “high” level the same amount of time that it is at a logical “low” level during each complete clock cycle). In present state-of-the-art semiconductor devices, the clock signal may have a frequency on the order of hundreds of megahertz.
A synchronous semiconductor device such as an SDRAM will typically require an external input signal such as a clock signal to be provided to several (or even numerous) separate but interrelated functional subcircuits of the device. As a matter of ordinary semiconductor device layout, it is typical for each of the separate subcircuits of an overall device to be physically disposed at different and perhaps distributed locations throughout the substrate as a whole. This means that the conductive lengths, and hence such characteristics as capacitive and complex impedance loads of the various conductive traces which carry electrical signals throughout the substrate, will vary from signal to signal. Hence, for example, the propagation delay of a clock signal from a clock signal input pin to one functional subcircuit may be different than the propagation delay to another functional subcircuit; such differences can be critical for devices operating at very high clock rates, on the order of 100 MHz or so (and perhaps less).
To address such considerations, an approach referred to as “delay-locked loop” or “DLL” can be employed.
FIG. 1
is illustrative of a simple example of DLL implementation. In
FIG. 1
, an externally-applied clock signal CLK is applied to an input pin
12
of a hypothetical memory device
10
. As shown in
FIG. 1
, the externally-applied CLK signal is applied to a DLL block
20
. DLL block
20
operates to derive a plurality of separate internal clock signals which are then provided to the various subcircuits of memory device
10
on lines
22
,
24
, and
26
. (Although only three internal clock signals are depicted in
FIG. 1
, those of ordinary skill will appreciate that more than three internal clock signals may be required in any given implementation.) The function of DLL block
20
(which may represent circuitry distributed throughout the area of the substrate, notwithstanding the centralized location represented for convenience in
FIG. 1
) is to adjust the relative timing of the clock signals provided on lines
22
,
24
, and
26
to the various distributed subcircuits of device
10
such that overall synchronous operation of the device
10
can be achieved.
DLL blocks such as DLL block
20
in
FIG. 1
may utilize some type of loop-back operation, as represented by exemplary dashed line
28
in
FIG. 1
, whereby DLL block
20
is provided with feedback for comparing the timing of the clock signal supplied on line
22
to command block
14
with the timing of incoming external clock signal CLK.
In the simplified example of
FIG. 1
, since command input buffer
14
and data input buffer
16
each receive and operate based on a clock signal, the command (CMD) input pin
15
and data (DATA) input pin
17
are said to be synchronous inputs. As such, binary data applied to input pins
15
and
17
will only be stored in the respective buffers
14
and
16
(a process sometimes referred to as “signal capture”) upon a rising or falling edge of the corresponding internal clock signal.
As a result of the functionality of a typical DLL circuit such as DLL block
20
in
FIG. 1
, if the propagation and loading characteristics of line
22
varies significantly from that of, say, lines
24
and
26
, DLL circuit can account for such differences in order to ensure that proper device operation can be maintained. Internally to DLL circuit
20
, separate delays and skews (programmable, or automatically adjusted) may be introduced into the externally-applied clock signal to ensure that each of the other functional blocks in device
10
receives clock signals that are substantially synchronized with the others. The delays and skews introduced by a DLL may be miniscule, on the order of picoseconds, but may be nonetheless critical to the proper operation of a semiconductor device.
The functionality of DLLs can be thought of generally as a process of internal clock signal generation, and those of ordinary skill in the art will doubtless be familiar at least generally with the concept of DLLs in semiconductor devices. Various examples of DLL implementations for synchronous memory devices are proposed in U.S. Pat. No. 5,920,518 to Harrison et al., entitled “Synchronous Clock Generator Including Delay-Locked Loo
Janzen Jeffrey W.
Johnson Brian
Keeth Brent
Manning Troy A.
Martin Chris G.
Browning & Bushman P.C.
Kress Hugh R.
Micro)n Technology, Inc.
Nguyen Nam
Nguyen Van Thu
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