Static information storage and retrieval – Addressing – Byte or page addressing
Patent
1988-06-16
1990-08-07
Hecker, Stuart N.
Static information storage and retrieval
Addressing
Byte or page addressing
365 78, 36518912, G11C 700, G11C 1142
Patent
active
049473808
ABSTRACT:
The invention relates to a memory device of the charge-coupled shift register type which is subdivided into four sections each of which has a storage capacity of, for example 208,800 bits and which can operate in different modes: parallel-in/parallel-out (as background video memory); 2.times.2 parallel-in, demultiplex/multiplex mode, for example for 100 Hz TV; scan mode; parallel-in-recirculation mode; "shortened" memory, for example for 525-line system, etcetera. Control is realized via a decoding and timing block in which a multi-bit control word is serially input and decoded. In a scan mode (for example, as a teletext memory), the memory sections are scanned one-by-one under the control of a separate scan register in which a scan bit (logic 1) is step-wise shifted until all sections have been read. Via a data output, the scan bit is transferred, for example to the scan register of a further memory device (via its serial data input) which is connected in series with the former memory device.
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Berkhoff et al., "Applications of Picture Memories in Television Receivers", IEEE Trans. Consum. Elec., vol. CE-29, No. 3, Aug. 1983, pp. 251-258.
Frencken Peter H.
Nillesen Antonius H. H. J.
Steenhof Frits A.
Van Der Sanden Cornelis G. L. M.
Van Zanten Adrianus T.
Barschall Anne E.
Bowler Alyssa H.
Briody Thomas A.
Haken Jack E.
Hecker Stuart N.
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