Radiant energy – Photocells; circuits and apparatus – Photocell controlled circuit
Reexamination Certificate
2002-04-30
2004-07-20
Allen, Stephone B. (Department: 2878)
Radiant energy
Photocells; circuits and apparatus
Photocell controlled circuit
C250S214100, C348S241000, C348S308000
Reexamination Certificate
active
06765186
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates to electronic imaging devices, and in particular to a CMOS imager incorporating a photoreceptor array and a multi-mode controller.
2. Related Art
Electronic imaging devices (“imagers”) find use in a broad range of applications in many distinct fields of technology including the consumer, industrial, medical, defense and scientific fields. Imagers use an array of photoreceptors to convert photons bearing image information into electrical signals representative of the image.
In recent years, CMOS imagers have become a practical implementation option and provide cost and power advantages over other technologies (such as charge coupled devices). A conventional CMOS imager is typically structured as an array of imager cells, each of which includes a photoreceptor approximately reset to a known potential in preparation for integration and readout of an image. The performance of a CMOS imager depends heavily on the performance of the individual imager cells.
In the past, the imager cells took the form of either passive photoreceptor cells, active photoreceptor cells, or transfer gate active photoreceptor cells. The passive photoreceptor cells typically included a photodiode for collecting photocharge and a single access transistor to connect the photodiode to a readout bus. However, passive photoreceptor cells, while having high quantum efficiency, were plagued by large amounts of noise.
As a result, imagers began to incorporate active photoreceptor cells. The active photoreceptor cells included a photoreceptor, and either three or four support transistors. The support transistors included a reset transistor, source follower transistor (for buffering and amplifying the collector photocharge), and an access transistor for connecting the photoreceptor to a readout bus. In transfer gate active photoreceptor cells, a fourth transfer gate transistor was used to transfer photocharge from the photoreceptor to a sense node, thereby allowing correlated double sampling, and a corresponding decrease in noise.
During integration, a photoreceptor cell sets up a potential well that collects electrons generated by incident photons. The potential well, however, has a limited charge capacity. As a result, it was possible for bright light to generate enough electrons to substantially fill the potential well of the photoreceptors in an imager, thereby yielding a washed out image. Thus, prior photoreceptor cells were not tailored to provide adequate response over a wide range of light levels.
Furthermore, prior imagers implemented a progressive readout technique that sequentially transferred charge from a row of photoreceptors to their respective sense nodes, then through respective amplifiers to a column bus. However, while one photoreceptor row was being readout, the image information stored in the remaining photoreceptor row was susceptible to noise from the photoreceptor structure itself, as well as from additional incident photons. Thus, the image acquired by the photoreceptor array changed as the image was being readout.
A need exists for an improved imager cell that addresses the problems noted above and other previously experienced.
SUMMARY
An improved imager is arrived at by incorporating a mulit-mode controller in an imager. The imager may be broadly conceptualized as an light detector with low noise characteristics that is configurable for a wide range of charge capacity, for a wide range of light levels, as compared to conventional imager cell implementations.
The imager may be implemented as an array of imager cells coupled to a multi-mode controller. The multi-mode controller includes circuitry that implements several modes of operation, including a high-light mode, a low-light mode, and a Snap mode. As explained in more detail below, the high-light mode provides charge accumulation in a photoreceptor potential well, a readout potential well, and a sense node potential well. The low-light mode provides charge accumulation in the photoreceptor potential well and constrained by an integration potential well. The Snap mode of operation simultaneously transfers accumulated charge for a set of the imager cells to their sense nodes.
During the high-light mode, the multi-mode controller applies a V+ integration voltage during an integration period to a photoreceptor readout gate, thereby allowing charge to accumulate in the readout potential well. In addition, the multi-mode controller may select one of a plurality of V+ integration voltages for setting up a selected charge capacity in one of the imager cells. Thus, the V+ integration voltage may be increased to provide charge capacity to address increased light levels.
The imager cells may be implemented using a pinned photoreceptor, a transfer gate, a reset transistor, an access transistor, and an output amplifier. The photoreceptor may be, for example, a photodiode. Furthermore, the imager cells may include anti-reflective coatings to improve performance.
Other implementations, methods, features and advantages of the invention will be or will become apparent to one with skill in the art upon examination of the following figures and detailed description. It is intended that all such additional systems, methods, features and advantages be included within this description, be within the scope of the invention, and be protected by the accompanying claims.
REFERENCES:
patent: 6166768 (2000-12-01), Fossum et al.
patent: 6320617 (2001-11-01), Gee et al.
patent: 6515702 (2003-02-01), Yadid-Pecht et al.
Allen Stephone B.
ESS Technology, Inc.
Farjami & Farjami LLP
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