Multi-master bus architecture for system-on-chip designs

Multiplex communications – Pathfinding or routing – Through a circuit switch

Reexamination Certificate

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C370S535000, C710S110000

Reexamination Certificate

active

07145903

ABSTRACT:
A bus architecture system to provide concurrency, fabricated on an integrated circuit for a system on chip design, for connecting a plurality of bus masters to a plurality of bus slaves. The system includes a plurality of multiplexers in communication with each data in port of each bus master and each bus slave. The system also includes a plurality of isolated data paths connecting the port out of each bus master to each multiplexer in communication with each data in port of each bus slave, and a plurality of isolated data paths connecting the port out of each bus slave to each multiplexer in communication with each data in port of each bus master, thereby providing concurrency on the system on chip design. In addition a distributed arbitration is included to allow each bus slave to be selected independently of the other bus slaves.

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