Multi-master bus arbitration system in which the address and dat

Details Multi-master bus arbitration system in which the address and dat Multi-master bus arbitration system in which the address and dat

1990-03-07

1996-09-10

Bowler, Alyssa H.

Boots, shoes, and leggings

395293, 36424292, 364DIG1, G06F 13362

Patent

active

055554253

ABSTRACT:
A multi-master digital computer system has a bus, a plurality of master devices connected to the bus, a plurality of slave devices connected to the bus, and a bus controller for arbitrating bus requests by the master devices and for granting the bus to a selected one of the plurality of the master devices. Each master device is capable of originating a bus cycle to transmit data to or receive data from a desired slave device. The bus controller grants the bus to a selected master device which enters an address master state and addresses the desired slave device. The selected master device is transferred to a bus master state where a data transfer to or from the slave device is initiated. The selected master device then transfers to a data master state unless the selected master device wants, and is permitted through an arbiter, to retain control of the bus. The bus controller grants a bus request to a requesting master device through to the arbiter. The requesting master device is transferred into the address master state while the selected master device is still in the data master state, thus performing a pipelining operation.

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