Multi-loop testing apparatus with field memory

Details Multi-loop testing apparatus with field memory Multi-loop testing apparatus with field memory

1992-04-09

1993-11-09

Kostak, Victor R.

Facsimile and static presentation processing

Facsimile

Specific signal processing circuitry

358335, 358 10, H04N 1706

Patent

active

052607844

ABSTRACT:
Apparatus for adjusting a digital signal which is subjected to analog processing after being reproduced from a record medium. A prerecorded digital test signal is reproduced and written to a field memory which, during a normal playback mode, is used to store the digital video signal that may be reproduced. A loop, which is opened during the normal playback mode, includes DAC and ADC for circulating the digital test signal therethrough a number of times and is coupled to the field memory to receive the stored test signal. A detector detects changes in the test signal after having been circulated through the loop, and these changes are used to establish adjustment settings for adjusting the digital video signal during a playback mode.

REFERENCES:
patent: 4682246 (1987-07-01), Efron et al.
patent: 5045950 (1991-09-01), Iwamura et al.

Affiliated with

Also associated with

Rating

Multi-loop testing apparatus with field memory does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Multi-loop testing apparatus with field memory, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Multi-loop testing apparatus with field memory will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-1146875