Multi-loop phase locked loop circuit

Details Multi-loop phase locked loop circuit Multi-loop phase locked loop circuit

2007-08-27

2009-11-24

Chang, Joseph (Department: 2817)

Oscillators

Automatic frequency stabilization using a phase or frequency...

Plural a.f.s. for a single oscillator

C331S010000, C331S016000, C331S060000

Reexamination Certificate

active

07622996

ABSTRACT:
Disclosed is a multi-loop PLL circuit and a related method of which, the circuit includes: a first loop for generating a first control current; a second loop for generating a second control current; a loop filter for generating a control signal according to the first control current or the second control current; a voltage control oscillator for generating a first oscillating signal or a second oscillating signal according to the control signal; a first frequency divider for generating a first feed back clock signal; a second frequency divider for generating a second feed back clock signal; and a control circuit for switching the first loop or the second loop to generate the control signal. The frequency of the second reference clock signal is higher than which of the first reference clock signal. The control circuit turns on the second loop first and then turns on the first loop.

REFERENCES:
patent: 5790942 (1998-08-01), Le Corre et al.
patent: 7061330 (2006-06-01), Kegasa et al.
patent: 2002/0136342 (2002-09-01), Lee et al.
patent: 2007/0035348 (2007-02-01), Self
Geum-Young Tak, et al., “A 6.3-9-Ghz CMOS Fast Settling PLL for MB-OFDM UWB Applications”, IEEE Journal of Solid-State Circuits, vol. 40, No. 8, Aug. 2005, pp. 1671-1679.

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