Multi-loop phase lock loop for controlling jitter in a high...

Details Multi-loop phase lock loop for controlling jitter in a high... Multi-loop phase lock loop for controlling jitter in a high...

2000-12-26

2003-03-25

Kinkead, Arnold (Department: 2817)

Oscillators

Automatic frequency stabilization using a phase or frequency...

Particular error voltage control

C331S00100A, C331S018000, C331SDIG002, C331S025000, C327S156000, C327S159000, C327S147000

Reexamination Certificate

active

06538518

ABSTRACT:

BACKGROUND OF THE INVENTION
A. Field of the Invention
The present invention relates generally to timing circuitry, and more particularly, to circuitry for high frequency clock alignment and switching.
B. Description of Related Art
Synchronous circuits are circuits that perform operations in step with a clock signal. For example, a clock source can be used in conjunction with a communication bus to provide a synchronous communications link between a sourcing device and one or more receiving devices. In a source synchronous communications link, the source device provides a source clock signal that the receiving device uses to synchronize the reading of data from the communications link.
Designs for mission critical systems must provide reliability. Redundancy can be built into a mission critical system to increase reliability. For example, redundant timing signals may be used in high performance telecommunications systems, such as high performance network routers. Such systems may include systems that have redundant, high frequency clock signals that receive and transmit data over optical carriers such as those conforming to the OC-48 or OC-192 synchronous optical network standard. In these systems, when an error is detected in the active clock, the redundant clock is switched to take over the role of the active clock.
Problems can arise when switching between high-frequency primary and redundant clock signals and when initially turning on the high-frequency clock signal. The high frequency of the clocks can make it difficult for the receiving system to obtain acquisition (“lock”) of the newly activated clock, because of the low phase-noise requirement of the high frequency clocks. Additionally, the high-frequency clock must filter jitter from the input reference clock signal. Finally, switch-over between the two clock signals may cause glitches.
Accordingly, there is a need in the art to be able quickly lock onto a new clock signal or a newly switched high-frequency clock signal while reducing jitter and glitches caused by clock signal cross-over.
SUMMARY OF THE INVENTION
Systems and methods consistent with the present invention address this and other needs through the use of a multi-loop phase locked loop.
More particularly, a first aspect of the present invention is directed to a redundant clock system comprising a number of elements, including input clock signals and a multiplexer connected to receive the input clock signals and a control signal. The multiplexer outputs one of the input clock signals as a reference clock signal in response to the control signal. Additionally, a phase locked loop circuit is connected to receive the reference clock signal from the multiplexer. The phase locked loop circuit includes a first loop filter and a second loop filter. The first loop filter has a first bandwidth for initially locking onto the reference clock signal. A second loop filter has a second bandwidth, less than the first bandwidth. The second loop filter corrects for jitter in the reference clock signal after the first loop filter has locked onto the reference clock signal.
A second aspect of the present invention is directed to a circuit for removing jitter from a high frequency clock signal. The circuit includes a lock detection component, a first loop filter, a second loop filter, a switch, and a voltage controlled oscillator. The first loop filter receives a signal based on phase differences between the reference clock signal and the feedback clock signal and has a first predetermined bandwidth. A second loop filter receives the signal based on phase differences between the reference clock signal and the feedback clock signal and has a second predetermined bandwidth lower than the first predetermined bandwidth. The switch selects, based on the lock detection signal from the lock detection component, either the first loop filter or the second loop filter as the active loop filter.
A third aspect of the present invention is directed to a method of generating a clock signal based on one of a number of input clock signals. The method includes selecting one of the input clock signals as a reference signal and generating a first signal based on phase differences between the reference clock signal and a feedback signal. First and second loop filters process the first signal. The first loop filter is designed to lock the feedback signal to a reference clock signal. The second loop filter reduces jitter in the locked signal.


REFERENCES:
patent: 4007429 (1977-02-01), Cadalora et al.
patent: 4920320 (1990-04-01), Matthews
patent: 5748569 (1998-05-01), Teodorescu et al.
patent: 6097777 (2000-08-01), Tateishi et al.
patent: 6259328 (2001-07-01), Wesolowski

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