Multi-level wiring structure of semiconductor device

Details Multi-level wiring structure of semiconductor device Multi-level wiring structure of semiconductor device

1988-04-25

1990-10-02

James, Andrew J.

357 51, 357 59, H01L 2348

Patent

active

049611046

ABSTRACT:
For preventing a thin wiring layer from destruction, a multi-level wiring structure incorporated in a semiconductor device is fabricated on a semiconductor substrate. It includes a first insulating layer formed on the semiconductor substrate, a first-level wiring layer of a first conductive material formed on the first insulating layer, a second insulating layer of a first insulating material covering the first-level wiring layer and having a first contact opening partially exposing the first-level wiring layer, a high-resistive second wiring layer formed on the second insulating layer in such a manner as to contact with the first-level wiring layer through the first contact opening and having a small thickness, a third insulating layer covering the high-resistive second wiring layer and having a second contact opening nested with respect to the first contact opening and partially exposing the high-resistive second wiring layer, and a third wiring layer formed on the third insulating layer in such a manner as to contact with the high-resistive second wiring layer through the second contact opening, wherein an etchant used for formation of the second contact opening has an etching rate for the first conductive material smaller than that for the first insulating material.

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