Multi-level voltage selection circuit

Details Multi-level voltage selection circuit Multi-level voltage selection circuit

1976-02-17

1977-07-26

Heyman, John S.

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

307209, 307243, 307270, 307DIG5, 340324M, 340336, H03K 1908, G02F 113, G08B 536

Patent

active

040385647

ABSTRACT:
A voltage selection circuit comprises CMOS circuits, each comprised of a series of P-channel MOS transistors and a series of N-channel MOS transistors. In each CMOS circuit, the gate electrodes of the P-channel MOS transistors are connected to those of the N-channel MOS transistors, respectively, to thereby form pairs of P- and N-channel transistors. Binary coded signals are supplied to the gate electrodes of the MOS transistors. In each CMOS circuit, upon receipt of binary coded signals at the pairs of P- and N-channel MOS transistors, only P-channel transistors or only N-channel transistors are turned on one after another. The voltage between the open source electrodes of each CMOS circuit can pass through the P-channel transistors or the N-channel transistors, thereby enabling selection of one of at least four different voltages based on the input binary coded signals.

REFERENCES:
patent: 3896430 (1975-07-01), Hatsukano
patent: 3900742 (1975-08-01), Hampel et al.
patent: 3903518 (1975-09-01), Hatsukano
patent: 3936676 (1976-02-01), Fujita
patent: 3945000 (1976-03-01), Suzuki et al.

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