Active solid-state devices (e.g. – transistors – solid-state diode – Non-single crystal – or recrystallized – semiconductor... – Field effect device in non-single crystal – or...
Patent
1998-04-28
1998-12-22
Saadat, Mahshid
Active solid-state devices (e.g., transistors, solid-state diode
Non-single crystal, or recrystallized, semiconductor...
Field effect device in non-single crystal, or...
257 74, H01L 2976, H01L 31112, H01L 31036
Patent
active
058523103
ABSTRACT:
A process is provided for producing active and passive devices on various levels of a semiconductor topography. As such, the present process can achieve device formation in three dimensions to enhance the overall density at which an integrated circuit is formed. The multi-level fabrication process not only adds to the overall circuit density but does so with emphasis placed on interconnection between devices on separate levels. Thus, high performance interconnect is introduced whereby the interconnect is made as short as possible between features within one transistor level to features within another transistor level. The interconnect employs a via routed directly between a well of an upper level transistor to a well of a lower transistor so as to effect direct coupling between the wells of the respective transistors. Direct coupling in this fashion affords consistent operation of transistors arranged on separate elevation levels. The via is made as short as possible so as to reduce any discrepancy in substrate/well voltage potential. This ensures predictable operation of transistors fashioned on separate elevation levels.
REFERENCES:
patent: 5470776 (1995-11-01), Ryou
patent: 5492851 (1996-02-01), Ryou
patent: 5606186 (1997-02-01), Noda
patent: 5610094 (1997-03-01), Ozaki et al.
Cheek Jon D.
Garnder Mark I.
Kadosh Daniel
Advanced Micro Devices , Inc.
Clark S. V.
Daffer Kevin L.
Saadat Mahshid
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