Multi-level shielded multi-conductor interconnect bus for MEMS

Details Multi-level shielded multi-conductor interconnect bus for MEMS Multi-level shielded multi-conductor interconnect bus for MEMS

2002-03-15

2004-06-08

Nhu, David (Department: 2818)

Active solid-state devices (e.g., transistors, solid-state diode

With shielding

C257S756000

Reexamination Certificate

active

06747340

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates generally to microclectromechanical systems (MEMS), and more particularly to the design and fabrication of interconnect architectures for MEMS.
BACKGROUND OF THE INVENTION
MEMS can include numerous electromechanical devices fabricated on a single substrate, many of which are to be separately actuated in order to achieve a desired operation. For example, a MEMS optical switch may include numerous mirrors that are each positionable in a desired orientation for reflecting optical signals between originating and target locations upon actuation of one or more microactuators associated with each mirror. In order for each mirror to be separately positioned, separate control signals need to be supplied to the microactuators associated with each mirror. One manner of accomplishing this is to connect each microactuator to a control signal source with a separate electrical conductor (i.e., an interconnect line) fabricated on the surface of the substrate that extends between its associated microactuator and a bond pad at the periphery of the substrate where it can be easily connected to an off-chip control signal source. In this regard, the separate interconnect lines together comprise an interconnect bus and are typically arranged to run parallel with each other for substantial portions of their length.
As may be appreciated, the amount of footprint required on the surface of the substrate for an interconnect bus is an important factor in designing MEMS since increasing the footprint of the interconnect bus decreases the amount of footprint available for desired devices (e.g., mirrors and actuators). Another consideration is possible cross-talk between the separate interconnect lines. Cross-talk is a problem because a control signal intended for one actuator can be coupled from its interconnect line into adjacent interconnect lines causing undesired actuation of other actuators. A further consideration is the possibility of shorting between adjacent interconnect lines. Where the interconnect bus lines are exposed on the surface of the substrate, particles and the like can settle across adjacent interconnect lines thereby causing short circuits effecting operation of the MEMS.
SUMMARY OF THE INVENTION
Accordingly, the present invention provides a shielded multi-conductor interconnect bus for MEMS and a method for fabricating such an interconnect bus. The shielded multi-conductor interconnect bus of the present invention substantially reduces the possibility of cross-talk between adjacent interconnect lines, alleviates the possibility of short circuits due to particles and the like settling across adjacent interconnect lines, and optimizes the amount of footprint required for such an interconnect bus.
According to a first aspect of the present invention, a multi-level shielded multi-conductor interconnect bus is provided having first and second levels of shielded electrically conductive lines. The second level electrically conductive lines may be oriented parallel with the first level electrically conductive lines or they may be oriented transverse to the first level electrically conductive lines. The multi-level shielded multi-conductor interconnect bus includes a substrate. The substrate may, for example, be comprised of silicon. A first dielectric layer overlies and is supported by at least a portion of the substrate. In this regard, the first dielectric layer may, for example, be the lowest layer of material on the substrate (i.e., it may be formed directly on the upper surface of the substrate without any intervening layers). In one embodiment, the substrate is comprised of silicon and the first dielectric layer comprises a dielectric stack deposited directly on the upper surface of the substrate that includes a lower layer of thermal oxide and an upper layer of silicon nitride. A plurality of substantially parallel first level electrically conductive lines are formed on the first dielectric layer. A first level electrically conductive shield is formed in a spaced relation above the first level electrically conductive lines. A plurality of first level electrically conductive walls are formed on the first dielectric layer. Although desirable, it should be understood that electrically conductive walls described herein do not have to be continuous along their lengthwise extent and may, in fact, have one or more breaks formed therein as desired. The first level electrically conductive walls typically extend parallel with the first level electrically conductive lines and include upper sections in contact along at least a portion thereof with a lower side of the first level electrically conductive shield. The first level electrically conductive lines and the first level electrically conductive walls are arranged in pattern such that at least one first level electrically conductive wall is located between sets of the first level electrically conductive lines, with each set of first level electrically conductive lines including at least one first level electrically conductive line.
The first dielectric layer may also include a plurality of first channels formed therein with lower sections of the first level electrically conductive walls being formed in the first channels. Where the first dielectric layer is the lowest layer of material on the substrate, each first channel preferably extends vertically downward through the entire thickness of the first dielectric layer along at least a portion of each first channel, and, more preferably along the entire length of each first channel to permit the lower sections of the first level electrically conductive walls to contact the upper surface of the substrate.
The multi-level shielded multi-conductor interconnect bus also includes a plurality of substantially parallel second level electrically conductive lines formed in a spaced relation above the first level electrically conductive shield. A second level electrically conductive shield is formed in a spaced relation above the second level electrically conductive lines. A plurality of second level electrically conductive walls are formed above the first level electrically conductive shield. The second level electrically conductive walls typically extend parallel with the second level electrically conductive lines and include lower sections in contact along at least a portion thereof with an upper side of the first level electrically conductive shield and upper sections in contact along at least a portion thereof with a lower side of the second level electrically conductive shield. The second level electrically conductive lines and second level electrically conductive walls are arranged in pattern such that at least one of the second level electrically conductive walls is located between sets of second level electrically conductive lines, with each set of second level electrically conductive lines including at least one second level electrically conductive line.
In one embodiment, the first level electrically conductive lines and the lower sections of the first level electrically conductive walls are formed from a first layer of doped polysilicon, the upper sections of the first level electrically conductive walls and the first level electrically conductive shield are formed from a second layer of doped polysilicon (which may be comprised of a thinner lower layer of doped polysilicon and a thicker upper layer of doped polysilicon), the second level electrically conductive lines and the lower sections of the second level electrically conductive walls are formed from a third layer of doped polysilicon, and the second level electrically shield and the upper sections of the second level electrically conductive walls are formed from a fourth layer of doped polysilicon.
The first and second level electrically conductive lines may be surrounded by dielectric material. In this regard, the multi-level shielded multi-conductor interconnect bus may also include second, third and fourth layers of dielectric material (e.g., silicon dioxide or silicate glass). T

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