Multi-level semiconductor structure and process of fabricating t

Details Multi-level semiconductor structure and process of fabricating t Multi-level semiconductor structure and process of fabricating t

1989-12-21

1990-11-13

Hearn, Brian E.

Fishing, trapping, and vermin destroying

437194, 437228, H01L 21447

Patent

active

049701770

ABSTRACT:
A multi-level semiconductor structure forming a part of a semiconductor device has a narrow wiring strip and a wide wiring strip formed on a lower insulating film, an inter-level insulating film structure covering the narrow and wide wiring strips, an upper insulating film provided on the inter-level insulating film structure and upper metal wiring strips formed on the upper insulating film and contacting respective contact areas of the narrow and wide wiring strips through contact holes formed through the upper insulating film as well as the inter-level insulating film structure, respectively, and the inter-level insulating structure consists of a first film deposited on the entire surface and a second film filling a gap between adjacent lower wiring strips for creating a smooth topography; the second film tends to be left on the wide wiring strip after an etch-back stage and is causative of erosion of the metal wiring strip, so that a plurality of moats are formed in the wide wiring strip for surrounding the contact area, thereby forming a narrow portion where no residual second film is left.

REFERENCES:
patent: 4696098 (1987-09-01), Yen
patent: 4839311 (1989-06-01), Riley et al.
patent: 4894351 (1990-01-01), Batty

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